Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

2016, Volume 17, Issue 9

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Frontiers of Information Technology & Electronic Engineering >> 2016, Volume 17, Issue 9 doi: 10.1631/FITEE.1500293

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou 310027, China

Available online: 2016-10-08

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Abstract

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.

Keywords

Low power ; Flip-flop ; Implicit ; Clock-gating scheme ; Dual-edge

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