Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

2020, Volume 21, Issue 4

Abstract

Keywords

Related Research

Frontiers of Information Technology & Electronic Engineering >> 2020, Volume 21, Issue 4 doi: 10.1631/FITEE.1800681

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

¹. Pune Institute of Computer Technology, Pune 411043, India
². Iziel Healthcare Pvt. Ltd., Pune 411028, India

Available online: 2020-05-13

HTML13 PDF 15 Collect 0

Next Previous

Abstract

Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resourceconstrained systems.

Keywords

Lightweight cryptography ; Internet of Things (IoT) ; Embedded security ; Encryption ; FPGA ; Datapath design

Related Research