cellular automata (QCA)%29&ck%5B%5D=abstract&ck%5B%5D=keyword'> is a new nanotechnology for the implementation of nano-sized digital circuits. This nanotechnology is remarkable in terms of speed, area, and power consumption compared to complementary metal-oxide-semiconductor (CMOS) technology and can significantly improve the design of various logic circuits. We propose a new method for implementing a in QCA technology in this paper. The proposed method uses the intrinsic features of QCA in timing and clock phases, and therefore, the proposed cell structure is less occupied and less power-consuming than existing implementation methods. In the proposed , compared to previous best designs, reductions of 6.45% in area occupation and 44.49% in power consumption were achieved. In addition, for the first time, a reset-based and a with set and reset capabilities are designed. Using the proposed , a new 3-bit is developed which reduces 2.14% cell numbers compared to the best of previous designs. Moreover, based on the 3-bit , a 4-bit is designed, which reduces 0.51% cell numbers and 4.16% cross-section area compared to previous designs. In addition, two selective s are introduced to count from 0 to 5 and from 2 to 5. Simulations were performed using and tools in coherence vector engine mode. The proposed circuits are compared with related designs in terms of delay, cell numbers, area, and leakage power.