Experimental Realization of Physical Unclonable Function Chip Utilizing Spintronic Memories

Xiuye Zhang , Chuanpeng Jiang , Jialiang Yin , Daoqian Zhu , Shiqi Wang , Sai Li , Zhongxiang Zhang , Ao Du , Wenlong Cai , Hongxi Liu , Kewen Shi , Kaihua Cao , Zhaohao Wang , Weisheng Zhao

Engineering ›› 2025, Vol. 49 ›› Issue (6) : 149 -157.

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Engineering ›› 2025, Vol. 49 ›› Issue (6) :149 -157. DOI: 10.1016/j.eng.2024.12.028
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Experimental Realization of Physical Unclonable Function Chip Utilizing Spintronic Memories
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Abstract

In recent years, physical unclonable function (PUF) has emerged as a lightweight solution in the Internet of Things security. However, conventional PUFs based on complementary metal oxide semiconductor (CMOS) present challenges such as insufficient randomness, significant power and area overhead, and vulnerability to environmental factors, leading to reduced reliability. In this study, we realize a strong, highly reliable and reconfigurable PUF with resistance against machine-learning attacks in a 1 kb spin-orbit torque magnetic random access memory fabricated using a 180 nm CMOS process. This strong PUF achieves a challenge–response pair capacity of 109 through a computing-in-memory approach. The results demonstrate that the proposed PUF exhibits near-ideal performance metrics: 50.07% uniformity, 50% diffuseness, 49.89% uniqueness, and a bit error rate of 0%, even in a 375 K environment. The reconfigurability of PUF is demonstrated by a reconfigurable Hamming distance of 49.31% and a correlation coefficient of less than 0.2, making it difficult to extract output keys through side-channel analysis. Furthermore, resistance to machine-learning modeling attacks is confirmed by achieving an ideal accuracy prediction of approximately 50% in the test set.

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Keywords

Physical unclonable function / Spin-orbit torque magnetic random access memory / Computing-in-memory / Reconfigurability / Machine-learning attack

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Xiuye Zhang, Chuanpeng Jiang, Jialiang Yin, Daoqian Zhu, Shiqi Wang, Sai Li, Zhongxiang Zhang, Ao Du, Wenlong Cai, Hongxi Liu, Kewen Shi, Kaihua Cao, Zhaohao Wang, Weisheng Zhao. Experimental Realization of Physical Unclonable Function Chip Utilizing Spintronic Memories. Engineering, 2025, 49(6): 149-157 DOI:10.1016/j.eng.2024.12.028

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1. Introduction

The exponential growth in the Internet of Things (IoT) has brought several challenges in hardware security. Predominantly constrained by cost considerations, IoT devices often lack robust encryption mechanisms [1], [2], [3]. This deficiency renders private data, such as the personal biometric information stored in nonvolatile memory (NVM), making it susceptible to unauthorized access and malicious attacks. This may subsequently result in the leakage of sensitive information and substantial economic repercussions. The physical unclonable function (PUF) has emerged as a promising and efficacious cryptographic primitive to mitigate these issues. In general, each PUF is characterized by a unique set of challenge–response pairs (CRPs). A specific “challenge” or input query to a PUF corresponds to a distinctive output or “response,” unique to each PUF instance. As a physical entity, it can serve as the root of trust for IoT devices, similar to a distinctive fingerprint or identity card [4], [5], [6], [7]. The PUF leverages the inherent randomness caused by variations in standard manufacturing processes. Such minute variations are manifested in several physical characteristics, including gate latency, threshold voltage, and the state trend of volatile memory once the device is powered on. The difficulty in replicating these manufacturing variations endows the PUF with a robust defense against cloning attempts. Unlike traditional hardware encryption methodologies such as digital signatures, PUF obviates the need for key storage in NVM or the incorporation of complex cryptographic hardware components. This characteristic not only significantly reduces energy consumption but also minimizes the spatial footprint of the encryption mechanism, making the PUF a lightweight solution for the security of IoT devices [8], [9], [10], [11].

Currently, the most prevalent implementations of all-electric PUFs rely on complementary metal oxide semiconductor (CMOS) technology, which can be broadly categorized into three types—static random access memory PUF [12], [13], [14], ring oscillator PUF [15], [16], [17], and regulated cascode current mirror PUF [18], [19], [20], [21]. However, CMOS PUFs possess several drawbacks, including substantial area overhead, limited randomness, and compromised reliability owing to environmental sensitivity, which hampers their feasibility in IoT applications. By contrast, emerging NVM-based PUFs are attracting interest in their potential widespread adoption in IoT applications due to characteristics such as low power and area requirements, abundant entropy sources (even within a single device), and relatively high reliability across diverse operational conditions [22], [23], [24], [25], [26], [27]. Among various NVM schemes, spin-orbit torque magnetic random access memory (SOT-MRAM), which is a third-generation magnetic random access memory (MRAM) technology, stands out due to factors such as compatibility with CMOS, fast writing and reading speed, and low energy demands [28], [29], [30], [31], [32]. Thus, PUFs based on SOT-MRAM are gaining traction as a potential technique in the field of IoT security.

In 2018, Chen et al. [33] pioneered the application of spin-orbit torque (SOT) devices in analog PUFs using a nonuniform etching process. This method induced a random magnetization orientation at the CoFeB/MgO interface, which extracted PUF CRPs by comparing the stochastic anomalous Hall resistance (RAHE). In subsequent studies, Finocchio et al. [34] and Zhang et al. [35] proposed a digital SOT PUF based on a perpendicular anisotropy device by exploiting the stochastic switching characteristic of magnetization along the easy axis. The PUFs were initialized by applying a sufficiently large current to align the magnetization in the in-plane direction. Upon current removal, the magnetization would randomly precess to the +z/−z-axis, yielding diverse RAHE outputs as responses. Moreover, the random distribution of magnetic domain wall pinning sites, which is attributable to process variations, was identified as an additional entropy source in SOT devices, enabling the generation of responses based on the RAHE values [36], [37], [38]. Several researchers introduced an antiferromagnetic film layer to facilitate field-free switching in devices and leveraged the switching polarity as a novel entropy source, thereby enhancing the reliability and robustness of PUFs [39], [40]. Despite these advancements, the prospects of these studies are limited due to the utilization of discrete Hall bar devices rather than chips, and the produced PUFs are weak PUF and susceptible to physical attacks (e.g., side-channel analysis and probing attacks) [41], [42] or machine-learning (ML) attacks [43], [44], which may result in leakage of sensitive information. In addition, the fixed nature of CRPs limits the reusability of PUF tokens, posing a threat to user privacy.

In this study, the previously outlined challenges are addressed by developing a strong, highly reliable, and reconfigurable PUF based on a 1 kb SOT-MRAM chip (SOT-MRAM sr-PUF) with resilience against several ML attacks, as shown in Fig. 1. The proposed PUF requires no additional chip design and can be implemented directly using memory chips. It is initialized by setting a specific writing voltage that balances the probabilities of high- and low-resistance states in the array to approximately 50%. Subsequently, a computing-in-memory (CIM) approach is employed to generate a 1-bit response by comparing the current summations according to different column combinations. The SOT-MRAM sr-PUF possess an extensive CRP (∼109) set, and all the performance metrics are near the ideal benchmarks. High reliability is achieved even without auxiliary techniques such as masking [8], [45], majority voting [24], [46] or error correction code [47]. The reconfigurability is successfully verified using the reconfigurable Hamming distance (HD) and correlation coefficient matrix. The resistance of the SOT-MRAM sr-PUF to ML modeling attacks is validated using logistic regression (LR), support vector machine (SVM), and multilayer perceptron (MLP) algorithms.

2. Experiments and methods

2.1. SOT-MRAM chip characterization

A 1 kb SOT-MRAM chip is fabricated using a 180 nm CMOS process. The top view of the chip under optical microscopy is shown in Fig. 2(a). The chip integrates a row/column address decoder, two banks of SOT magnetic tunnel junction (MTJ) arrays, and a multiplexer circuit. Fig. 2(b) shows the basic cell of the SOT-MRAM, which consists of a type-Y SOT-MTJ with three transistors. The read word line (RWL), which is attached to the top of the SOT-MTJ, controls the read signal, whereas the write word line (WWL) and write word line bar (WWLB), which are connected to the heavy metal layer, control the write signal. The 3T1R layout design suppresses sneak current paths, reducing the errors in the subsequent CRP extraction process. Details of the SOT-MTJ stack composition and device characteristics are discussed in previous studies [48], [49]. Discrepancies in the manufacturing process cause variations in the switching threshold voltages across the array, leading to a unique resistance distribution generated by specific write voltages. The subtle discrepancies in manufacturing processes exhibit inherent uncontrollability. Three 1 kb SOT-MRAM chips are fabricated to verify the repeatability of switching threshold voltage variations in different chips as shown in Appendix A Figs. S1(a)–(c), and the resistance of all units in the array as a function of applied voltage (R–V curves) on each chip are shown in Appendix A Fig. S1(d)–(f). Fig. 2(c) shows the cumulative distribution function (CDF) of the switching threshold voltage in two scenarios—flipping from the parallel (P) state to the antiparallel (AP) state, and vice versa. These data are statistically derived from the R–V curves shown in Fig. S1(d). An endurance test was also conducted on six randomly selected devices from across the array, as shown in Fig. 2(d). After a write pulse of 1.5 V/100 ns was applied for up to 1011 cycles, all the devices maintain stable resistance states, demonstrating that the chip possesses a long lifespan and good reliability. Additional details of the other six devices before and after the endurance test are provided in Appendix A Fig. S2.

2.2. Design scheme of PUF CRPs

The SOT-MRAM sr-PUF CRPs can be extracted in two steps—PUF initialization and generation of CRPs. In PUF initialization, a reset voltage pulse of ±1.5 V/100 ns is initially applied to all bit cells in the array to set them to either high resistance state (HRS) or low resistance state (LRS). The HRS setting is depicted in Fig. 3(a). Subsequently, a specific writing pulse voltage (i.e., 0.9 V/100 ns) is applied to the PUF to achieve a uniform distribution of HRS and LRS across the array, and the resulting resistance distribution is shown in Fig. 3(b). The reference current is set to the median of the current distribution for all units under a reading voltage of 0.1 V. To minimize the effects of intermediate states on the PUF performance, a writing back operation is performed on each unit. If the reading current of a cell exceeds (or falls below) the reference current, it is reset to LRS (or HRS), as shown in Fig. 3(c). In the CRPs generation step, a CIM approach is employed, as shown in Fig. 3(d). The method for extracting a 1-bit response begins with the selection of 16 different columns in the array. The reading voltage is then applied to all rows over two cycles. The sums of the currents from the selected and remaining columns are recorded in registers 1 and 2, respectively. A 1-bit response is then generated based on a comparison of the current summation from the two cycles. A timing diagram of this process is shown in Fig. 3(e). To clearly express the CRP in this article, the selection status of the column addresses is used as the challenge. The challenge involves a 32-bit binary number (where a selected column is represented by “1” and an unselected column is represented by “0”), and the corresponding responses are represented as a 1-bit binary digit (0 or 1).

3. Results and discussion

3.1. SOT-MRAM sr-PUF performance evaluation

To date, the performance of a PUF instance is typically evaluated based on four key metrics—uniformity (UF), reliability, diffuseness (DF), and uniqueness (UQ) [23], [27]. In this section, the randomness in PUF output is analyzed. For brevity in subsequent sections, the function F(·) is defined to compute the number of “1’s” in each response, and rbits represents the number of bits per response. The key length in all the subsequent tests is 256 bits.

The assessment of UF involves calculating the HD, which counts the number of “1’s” in a binary string. However, a direct comparison of HD between different PUFs is complicated due to the diversity in response lengths. Therefore, fractional HD, defined as the probability of “1” in each response, is generally employed to evaluate the UF. Ideally, UF should be 50% to ensure that there is no deviation in the probability of the response producing “1” and “0.” UF is calculated using the equation shown below:

$\mathrm{UF}=100\%\times\sum_{i=1}^NF(r_i)/(N\times r_{\mathrm{bits}})$

where N denotes the total number of CRPs and ri represents the corresponding responses.

Fig. 4(a) shows the frequency distribution of the fractional HD of UF obtained from 10 000 keys. The total response length under normal test condition is 2.56 million bits (reading voltage 0.1 V/100 ns, operating temperature 300 K). The pink dashed line, resulting from Gaussian fitting, indicates a very tight normal distribution with a standard deviation (σ) of 6.41%, centered around a mean (μ) of 50.07%. This suggests that the “1’s” in the PUF responses are uniformly distributed, achieving a nearly ideal value of UF.

Reliability metrics are used to evaluate the stability of a PUF entity. When utilized as encryption keys, the PUF responses necessitate ultrahigh stability—that is, applying the same challenge to the same PUF entity under varying environmental conditions should ideally yield identical responses. However, environmental fluctuations such as changes in the power supply voltage or operating temperature, may induce bit flips in the reproduced responses. These variations can be quantified using native bit error rate (BER) [25], [26]. Fig. 4(b) displays the BER results of both the resistance values in the array and the 1000 output responses, spanning a temperature range from 235 to 375 K. Due to write-back operation, the BER values in the SOT-MRAM sr-PUF are exceptionally low and close to the ideal value of 0, demonstrating high reliability. Furthermore, the intra-HD is employed to quantify the output key error further based on the BER results, aiming for an ideal value of 0. Intra-HD is defined by Eq. (2):

$\mathrm{Intra-HD}=100\%\times\sum_{i=1}^{N_\mathrm{cycles}-1}\sum_{j=i+1}^{N_\mathrm{cycles}}F(m_i\oplus m_j)/\left(C_{N_\mathrm{cycles}}^2\times r_\mathrm{bits}\right)$

where Ncycles represents the number of tests conducted under varied conditions, and mi and mj are the PUF responses obtained from the ith and jth tests, respectively, given the same challenge.

Because a strong PUF chip can generate numerous CRPs, DF is used to assess the variability among responses to different challenges within the same PUF instance. DF is typically measured using the inter-HD, which is the count of “1’s” resulting from the XOR operation between two responses, with the ideal value at 50%. The DF can be quantified using Eq. (3):

$\mathrm{DF}=100\%\times\sum_{i=1}^{N_\text{challenges}-1}\sum_{j=i+1}^{N_\text{challenges}}F(n_i\oplus n_j)/\left(C_{N_\text{challenges}}^2\times r_\mathrm{bits}\right)$

where Nchallenges represents the number of challenges input to the PUF entity, and ni and nj denote the responses from the ith and jth challenges, respectively.

Fig. 4(c) shows a histogram of the fractional HD of DF extracted from 1000 keys (the total HD is 499 500) under normal test conditions. Gauss fitting reveals an almost ideal distribution with a mean (μ) of 50% and a standard deviation (σ) of 6.52%, indicating significant variability between keys extracted from the same chip.

Ideally, two distinct PUFs should produce significantly different responses to the same challenge. The metric used to assess the distinctiveness between PUF entities is UQ, with the ideal value set at 50%. The UQ is calculated in a manner similar to that for DF and is defined by Eq. (4):

$\mathrm{UQ}=100\%\times\sum_{i=1}^{N_{\mathrm{chip}}-1}\sum_{j=i+1}^{N_{\mathrm{chip}}}F(d_i\oplus d_j)\left/\left(C_{N_{\mathrm{chip}}}^2\times r_{\mathrm{bits}}\right)\right.$

where Nchip represents the total number of PUF entities, and di and dj denote the responses of the ith and jth PUF entities, respectively.

Fig. 4(d) shows the statistical results of UQ extracted from five chips, with each subjected to the same 1000 challenges under standard test conditions. The Gaussian fitting of the fractional HD demonstrates an almost ideal distribution with a mean (μ) of 49.89% and a standard deviation (σ) of 12.62%, indicating excellent UQ properties. Furthermore, intra-HD is calculated based on the outcomes of reliability assessment. The near-infinite inter-HD/intra-HD ratio suggests that the proposed PUFs exhibit ideal characteristics.

NIST SP800-22 is an extensively used test suite that consists of 15 tests for evaluating the randomness of binary sequences. In this research, except for the parameter in the non-overlapping template test, which is changed to 10 (to obtain more statistically meaningful results), all default parameters are used. The test results of a 2.56 Mbit response stream extracted from the SOT-MRAM sr-PUF without postprocessing (i.e., raw data) are shown in Fig. 4(e). All test indicators are passed, indicating sufficient randomness for practical cryptographic applications. Furthermore, the spatial correlation of the PUF response can be quantitatively evaluated using the autocorrelation function (ACF) test. Fig. 4(f) shows the ACF test result of a 2.56 Mbit length response. The results show that a majority of the data points are within the confidence range interval, which indicates that the input response sequence has no spatial correlation until the lag length reaches 5000. A very small ACF value (average less than 0.002) indicates that the entropy source has similar behavior to ideal white noise. This result indicates that the responses generated by the SOT-MRAM sr-PUF are an independent variable, making it nearly impossible for potential attackers to infer new CRPs from known ones.

3.2. SOT-MRAM sr-PUF attack resistance

The CRPs of PUFs are typically immutable once initialized, limiting their application in untrusted environments. To counter potential attacks, such as side-channel analysis, an update mechanism based on the change in write voltage is developed. This mechanism helps realize a reconfigurable PUF that can dynamically refresh CRPs, rendering any data collected by attackers obsolete.

The distributions of HRS and LRS across the array can be modulated by applying different write voltages. To demonstrate reconfigurability, ten reconfiguration cycles are conducted on the same PUF chip using ten different amplitude voltages. The write voltage for the first five cycles range from −0.46 to −0.5 V, with 0.01 V increments, and it induces a transition from HRS to LRS. Conversely, for cycles 6–10, the voltage range from 0.59 to 0.63 V, transitioning from LRS back to HRS. Upon completion of each reconfiguration cycle, a reset voltage is applied to set all array units uniformly to either HRS or LRS. The CRPs generated during these cycles exhibit the same high-quality performance as that of those generated initially. To quantify the variability of the CRPs across different cycles, a new metric, reconfigure-HD (Re-HD), is introduced to assess the reconfigurability. Re-HD is defined by Eq. (5):

$\mathrm{Re-HD}=100\%\times\sum_{i=1}^{M_{\mathrm{cycles}}-1}\sum_{j=i+1}^{M_{\mathrm{cycles}}}F(\mathrm{re}_i\oplus\mathrm{re}_j)/\left(C_{M_{\mathrm{cycles}}}^2\times r_{\mathrm{bits}}\right)$

where Mcycles represents the number of reconfiguration cycles implemented, and rei and rej denote the PUF responses obtained from the ith and jth reconfiguration cycles, respectively, under varying write voltages.

By applying the same 1000 challenges across ten different cycles on a single chip, a Re-HD distribution is obtained with a total HD of 45000. The corresponding Gaussian fitting, shown in Fig. 5(a), displays a nearly ideal distribution with a μ value of 49.31%, closely approximating the ideal value of 50%. This analysis indicates that the CRPs generated in different cycles significantly differ from each other. Pearson’s correlation coefficients are calculated to analyze the correlation between the responses from different reconfiguration cycles. Fig. 5(b) shows the correlation matrix for ten cycles, revealing that the correlation coefficients for the various reconfigured responses are significantly less than 0.2, indicating a lack of correlation. These findings demonstrate the effective implementation of a reconfigurable PUF that can successfully generate uncorrelated CRPs.

Furthermore, the conditional probability that bi+1 = n given bi = m is calculated, denoted as Pr(bi+1 = n|bi = m), where bi+1 and bi represent the bits in rei+1 and rei, respectively, and m and n are either 0 or 1. This probability is essential for determining the min-entropy H∞, which quantifies the entropy loss between different cycles, as shown in Eq. (6) [25]:

$H_\infty(b_{i+1}|b_i)=-\log\{E_{m\leftarrow b_i}[\max_n\Pr[b_{i+1}=n|b_i=m]]\}$

where E is the symbol for expectation.

Conditional min-entropy evaluates the extent of information preservation when ri is reconfigured to ri+1. A conditional min-entropy of 0 indicates that bi+1 can be easily predicted from bi, implying high predictability. Conversely, a conditional min-entropy of 1 suggests that bi reveals no information related to bi+1, indicating optimal unpredictability. The conditional min-entropy value between adjacent cycles is shown in Fig. 5(c). The average value is 0.88, indicating that the PUF exhibits strong security. This indicates that the likelihood of an attacker correctly guessing the reconfigured 256-bit key based on a deciphered key is less than 2−256×0.88 = 1.5 × 10−68. Given the computational speed of state-of-the-art supercomputers, which exceeds 2 × 105 tera floating-point operations per second (TFlop·s−1), it would still take tens of thousands of years to crack this key, rendering such an attempt practically unfeasible [24].

Because a PUF can be summarized as a function with many unknown parameters, ML algorithms can efficiently approximate these functions and decipher the PUF by mathematically modeling its intrinsic parameters. For strong PUFs, where the verification process of CRPs is publicly available, attackers can collect a subset of CRPs to build a numerical model and accurately predict the remaining unknown CRPs, thereby compromising security. Specifically, ML algorithms frame the PUF output as a classification task and use supervised learning models to capture the underlying features of the PUF [43], [50].

To evaluate the ML attack resistance of the 1 kb SOT-MRAM sr-PUF, three ML algorithms, namely LR, SVM, and MLP, are employed to train CRP models with sizes ranging from 100 to 2 million pairs and to output prediction accuracy on a test set. All models are set up in a Python environment with a training-to-test-set ratio of 4:1, and fivefold cross validation is used to enhance the robustness of the test results. The LR algorithm is implemented using the LIBLINEAR library, and the SVM algorithm is implemented using the LIBSVM library with a radial basis function kernel. The MLP algorithm is implemented by constructing a 32 × 64 × 16 × 1 neural-network architecture with a rectified linear unit function as the activation function in the two hidden layers. As depicted in Fig. 5(d), the experimental results demonstrate that the prediction accuracy of the 1 kb SOT-MRAM sr-PUF is close to the ideal value of approximately 50% under all three ML attack algorithms, indicating a robust resistance to ML attacks. Furthermore, detailed comparisons of the performance parameters of the 1 kb SOT-MRAM sr-PUF with state-of-the-art PUFs from recent years are provided in Appendix A Table S1.

4. Conclusions

A 1 kb SOT-MRAM chip based on a 180 nm CMOS technology is fabricated, and an sr-PUF is implemented. Specific write operations generate a unique resistance distribution on the chip, thereby achieving a strong PUF through a CIM approach. All performance parameters of the 1 kb SOT-MRAM sr-PUF approach ideal values, and it demonstrates excellent environmental stability even without additional auxiliary techniques. The reconfigurability of the PUF is achieved by applying different write voltages, and the dynamically refreshable CRPs provide high resistance to side-channel attacks. Furthermore, the PUF is immune to three different ML attacks, underscoring its robust security performance. These contributions significantly advance the domain of SOT MRAM-based PUFs and offer a viable and promising hardware security solution for future IoT applications.

CRediT authorship contribution statement

Xiuye Zhang: Writing – review & editing, Writing – original draft, Visualization, Validation, Software, Resources, Methodology, Investigation, Formal analysis, Data curation, Conceptualization. Chuanpeng Jiang: Writing – review & editing, Validation, Formal analysis, Data curation. Jialiang Yin: Writing – review & editing, Validation, Formal analysis. Daoqian Zhu: Writing – review & editing, Validation, Formal analysis. Shiqi Wang: Validation. Sai Li: Validation. Zhongxiang Zhang: Validation. Ao Du: Writing – review & editing, Validation, Funding acquisition. Wenlong Cai: Writing – review & editing, Validation, Formal analysis. Hongxi Liu: Writing – review & editing, Validation, Formal analysis, Data curation. Kewen Shi: Writing – review & editing, Validation. Kaihua Cao: Validation. Zhaohao Wang: Validation. Weisheng Zhao: Writing – review & editing, Validation, Supervision, Project administration, Funding acquisition, Formal analysis, Data curation.

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (92164206, 52261145694, T2394474, T2394470, 623B2015, 62271026, 62401026, and 62404013), the National Key Research and Development Program of China (2022YFB4400200), the New Cornerstone Science Foundation through the XPLORER PRIZE, the National Postdoctoral Program for Innovative Talents (BX20220374 and BX20240455), and the China Postdoctoral Science Foundation Funded Project (2023M740177 and 2022M720345).

Appendix A. Supplementary data

Supplementary data to this article can be found online at https://doi.org/10.1016/j.eng.2024.12.028.

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