The previously slow and steady rise in the adoption of a streamlined computer chip instruction set architecture (ISA), the fifth generation of reduced instruction set computer (RISC-V), has officially entered overdrive. In early February 2022, the silicon heavyweight Intel (Santa Clara, CA, USA) announced a big investment in the RISCV ecosystem, part of a 1 billion USD fund launched by Intel to support partnerships between it and other companies developing new chip-based technology[1–2]. The move bolsters Intel’s plans to grow its foundry business and is complemented by the company’s simultaneously announced new membership in RISC-V International, the Zurich, Switzerland-based organization that governs the codification of the core and new extensions for RISC-V, a freely available, open-standard ISA first introduced in 2010[1–2].
‘‘Intel partnering with several RISC-V members is a huge signal to the industry about the growing interest and adoption of RISC-V,” said Calista Redmond, chief executive officer of RISC-V International. ‘‘Intel recognizes that RISC-V will be a critical component for the success of its foundry endeavors, so the company is investing heavily in making it easier for companies to design RISC-V solutions.”
The RISC-V market, though still relatively small, is expected to grow rapidly. The consulting and analytics firm Deloitte Global (New York City, NY, USA) predicts the market for RISC-V processing cores will double in 2022 compared to 2021 and double again in 2023 [3]. RISC-V revenue will increase more slowly, though, nearing 800 million USD in 2023, up from less than 400 million USD in 2021, and approaching 1 billion USD by 2024 [3].
At a basic level, the ISA in chips allows software to directly control hardware, and the chips that now drive most of the world’s devices use two well-established—and proprietary—ISAs. Over the past several decades, Intel’s x86 has maintained its position as the dominant ISA used in the chips in laptops, desktops, and server hardware. In contrast, most smartphones use ARM-based chips, primarily because they consume little power. But now a growing contingent of companies in the United States, Europe, and especially Asia sees RISC-V as an attractive alternative—and supplement—to these entrenched standards.
RISC-V is one of many RISC-based ISAs, including ARM, created over the years, for which four individuals were awarded the 2022 Charles Stark Draper Prize in March [4]. The moniker ‘‘reduced instruction set computer” reflects the aim of the prize recipients—Stephen B. Furber, professor of computer engineering at the University of Manchester, UK; John L. Hennessy, professor of computer science and electrical engineering at Stanford University in Palo Alto, CA, USA; David A. Patterson, professor emeritus at the University of California, Berkeley, CA, USA; and Sophie M. Wilson, a Cambridge University, UK-trained computer scientist— and their many collaborators to build smaller, lower-power but better-performing processors by decreasing the complexity of the core set of executable instructions [4]. With RISC-V, the result is a core of 47 instructions—paltry compared to x86’s 1000-some instructions and ARM’s roughly 500[2–5]. And RISC-V is an extensible ISA, meaning that companies can implement the instruction set core and later expand it by adding defined extensions or creating their own to build bespoke processors.
This makes RISC-V-based chip designs easy to modify, allowing for greater flexibility when applied to the broad range of digital applications, from high-performance computing (HPC), self-driving vehicles and the Internet of Things (IoT) to storage, graphics, and artificial intelligence (AI) and machine learning [3]. ‘‘RISC-V is fairly sophisticated. It does not have 30 years of baggage, which makes it a ‘clean-slate’ architecture,” said Balaji Baktha, chief executive officer and founder of RISC-V processor developer—and one of several new Intel partners—Ventana Micro Systems in Cupertino, CA, USA.
In addition to offering flexibility, being open standard also makes RISC-V an attractive option, particularly for startups wanting to design custom chips without spending the millions of dollars in license fees required to use proprietary chip architectures. Both factors have been cited as making RISC-V an increasingly popular chip architecture for companies such as the computing storage giants Seagate (Cupertino, CA, USA) and Western Digital (San Jose, CA, USA), as well as e-commerce giant Alibaba (Hangzhou, China) [6].
Being open standard also makes RISC-V appealing to companies that have lost or fear losing access to x86 or ARM, potentially due to export restrictions [7]. Choosing RISC-V eliminates that issue. Chinese companies make up more than a third of the membership of RISC-V International, including, among others, Huawei (Shenzhen, China) and Alibaba Cloud, with multiple large Chinese companies having announced their intention to use RISC-V chips [6]. In addition, China launched a research institute in late 2021 devoted to RISC-V processor projects [8], Alibaba announced efforts to port Android to RISC-V [9], and a pair of Chinese firms—DeepComputing and Xcalibyte—have begun manufacturing the world’s first RISC-V-based laptop in Shenzhen, China [10].
By climbing aboard the RISC-V bandwagon, Intel aims to help RISC-V development-focused companies, including announced partners Andes Technology (Hsinchu, China), Esperanto Technologies (Mountain View, CA, USA), SiFive (San Mateo, CA, USA), and Baktha’s VentanaMicro Systems,more quickly innovate by prioritizing their manufacturing runs and working with them to co-develop manufacturing technology that optimizes their designs[1–2].
A primary goal of Intel’s 1 billion USD fund is to implement a cost-effective modular design that integrates several types of processor cores within an individual chip package[1–2]. This will help the chip giant’s new venture, Intel Foundry Services, manufacture chips that each contain multiple chiplet dies, with custom mixes of x86, ARM, and RISC-V cores. ‘‘People ask if Intel sees RISC-V as a threat,” Baktha said. ‘‘Their investment shows otherwise. Allowing RISC-V to sit alongside x86 infrastructure makes things like data center innovation happen at a level never before possible.”
Much of the interest in RISC-V is coming from demand for AI applications. For edge-based AI implementations where AI processes run and generate data on local devices like laptops, rather than in the cloud, ‘‘computing and AI need to come together in a unified architecture,” said Baktha. ‘‘RISC-V is the only way to do it.” Semiconductor consulting firm Semico Research (Phoenix, AZ, USA) estimates that RISC-V-based AI systems-on-a-chip (SoC)— integrated circuits consisting of all or most components of a computer—will see an average of 74% growth per year between now and 2027 [11]. Semico additionally projects RISC-V AI SoC for consumer IoT solutions to grow 140% per year over the same timeframe, along with 98% yearly growth for HPC markets like data center servers [11].
When initially released in 2010, RISC-V lacked the vector instructions required for the math of machine learning, including matrix multiplication. To overcome this gap, Esperanto engineers developed their own instructions, which they have incorporated into their new chip, the ET-SoC-1 (Fig. 1), marketed by the company as the first high-performance RISC-V AI chip [2]. The company specifically designed the ET-SoC-1 for power-efficient inference processing and to compete against powerful graphics processing unit (GPU) in AI-recommendation systems (which offer relevant suggestions to users based on data such as their demographics or prior behavior), primarily for e-commerce and social media firms [12]. At half the size of its primary competition, Nvidia’s A100 chip, the ET-SoC-1 draws just one tenth the power of the A100 [2]. Several companies, including Samsung, are now exploring the use of the ET-SoC-1 in their devices [13].
Fig. 1. Esperanto Technologies’ ET-SoC-1 chip packs more than 1000 RISC-V cores onto a 570 mm2 piece of silicon that consumes just 20 W in operation. Credit: Esperanto Technologies (public domain).
Other companies with recently developed AI processors are using combinations of RISC-V and custom machine-learning acceleration technology. For example, the Hierarchical Learning Processor announced in January 2022 by San Jose, USA-based Ceremorphic combines RISC-V and ARM cores along with its own custom machine-learning and floating-point arithmetic units [14]. And Intel’s forthcoming Mobileye EyeQ Ultra will have 12 RISC-V cores supplemented by proprietary neural-network accelerators, along with an ARM CPU, in a chip meant to supply intelligence for near fully autonomous driving [15]. Also turning to RISC-V to support autonomous driving is embedded AI processor firm Kneron (San Diego, CA, USA). Last November, the company began mass-producing its first RISC-V KL530 chip based on a new type of neural network that performs image classification tasks [16].
In June 2022, Intel, which already offers RISC-V-based Nios V processors, announced a collaboration with the Barcelona Supercomputing Centre in Spain to build a 400 million USD facility devoted to developing RISC-V processors for HPC, as well as specialized chips for AI and autonomous vehicles. A primary goal of the collaboration is to create zettascale systems 1000-times more powerful than today’s fastest supercomputers, a milestone that Intel says it aims to achieve within the next five years[17,18].
While the future of RISC-V appears bright, several challenges remain for developers before the market can fully embrace the ISA [3]. Certain kinds of new RISC-V-based software compilers, processors, and computer designs must be built de novo, a timeconsuming and expensive prospect. Also, while RISC-V is supported by several distributions of Linux, including Ubuntu, Debian, FreeBSD, NetBSD, and OpenBSD, it has yet to be adapted for some other widely used operating systems.
Regardless, like many of its promotors, Redmond focuses on the flexibility she sees RISC-V bringing to the world of computing. ‘‘For decades, custom silicon was only attainable for companies with huge design teams and budgets,” Redmond said. ‘‘RISC-V enables design freedom across every domain and industry, making it possible for companies of all sizes to push the bounds of innovation and have an opportunity to compete.”