在三维（3D）堆叠中，硅通孔（TSV）的热应力对芯片性能和可靠性有显著影响，这一问题在高密度TSV阵列中更为突出。本研究提出并开发了一种新型空心钨TSV（W-TSV）。其空心结构为热应力释放提供了空间。仿真结果表明，空心W-TSV在距衬底表面顶部2 μm范围内可释放60.3%的热应力，在3 μm径向区域内，热应力可降至20 MPa以下。制备了尺寸为640 × 512、间距为25 μm、深宽比为20.3∶1的超高密度（1600 TSV∙mm^-²）TSV阵列。测试结果显示，所制备的TSV具有优异的电学和可靠性性能。TSV的平均电阻为1.21 Ω，漏电流为643 pA，击穿电压大于100 V。在经历-40~125 ℃的100次温度循环后，电阻变化小于2%。拉曼光谱分析表明，空心W-TSV在晶圆表面产生的最大应力为31.02 MPa，证明所制造的高密度TSV阵列不需要设置禁止放置晶体管的区域（KOZ）。这些结果表明，该结构在大阵列光电探测器和3D集成电路中具有巨大的应用潜力。

In three-dimensional (3D) stacking, the thermal stress of through-silicon via (TSV) has a significant influence on chip performance and reliability, and this problem is exacerbated in high-density TSV arrays. In this study, a novel hollow tungsten TSV (W-TSV) is presented and developed. The hollow structure provides space for the release of thermal stress. Simulation results showed that the hollow W-TSV structure can release 60.3% of thermal stress within the top 2 μm from the surface, and thermal stress can be decreased to less than 20 MPa in the radial area of 3 μm. The ultra-high-density (1600 TSV∙mm⁻²) TSV array with a size of 640 × 512, a pitch of 25 μm, and an aspect ratio of 20.3 was fabricated, and the test results demonstrated that the proposed TSV has excellent electrical and reliability performances. The average resistance of the TSV was 1.21 Ω. The leakage current was 643 pA and the breakdown voltage was greater than 100 V. The resistance change is less than 2% after 100 temperature cycles from −40 to 125 °C. Raman spectroscopy showed that the maximum stress on the wafer surface caused by the hollow W-TSV was 31.02 MPa, which means that there was no keep-out zone (KOZ) caused by the TSV array. These results indicate that this structure has great potential for applications in large-array photodetectors and 3D integrated circuits.