1. Introduction
Fifth-generation (5G) wireless communication aims to provide high mobile data and low latency to meet various use cases, such as streaming video, augmented reality, playing three-dimensional (3D) games, automotive driving, and massive machine-type communication. Such requirements pose a key challenge for 5G front-end systems to feature large available bandwidths. According to the third Generation Partnership Project (3GPP) release, several spectra in millimetre wave (mmWave) bands have been issued for 5G new radio (NR), such as 28 and 39 GHz bands, which are extensions of the sub-6 GHz frequency range [
1]. Due to the huge commercial market potential, 5G mmWave transceivers based on lowcost complementary metal-oxide semiconductor (CMOS) technologies have attracted tremendous attention from academic and industrial fields[
2–
7].
However, 5G mmWave communication systems suffer from higher free-space path loss and lower diffraction because of the smaller wavelengths[
8–
9]. Fortunately, the mmWave frequency facilitates high-gain antenna design by using an array with a large element number, which can compensate for the path loss to some extent. To meet the mobile demand, the 5G NR should also have beamforming and beam-scanning functionalities. To tackle the aforementioned technical challenges, some efforts have been made in the implementation of CMOS phased-array transceivers and related circuit techniques around 28 and 39 GHz in recent years [2–7,10–17]. Digital beamforming transceivers[
5,
16] and hybrid beamforming-based front-ends[
6–
7] feature high-performance beamforming and beam scanning; whereas, these systems are challenged by tremendous signal processing and hence require powerand area-hungry wideband digital processors. Refs. [3,11,12,18] introduce 28 GHz CMOS phased-array transceivers based on radiofrequency (RF) phase-shifting architectures as shown in Fig. 1(a), they achieve high integration. However, the phase/amplitude tuning in each RF channel will result in additional amplitude/phase variation, thereby deteriorating the performance of the entire system, particularly in their beamforming and beam-scanning accuracy. Additionally, over-the-air (OTA) testing and calibration for large-scale phased-array systems are time-consuming and expensive[
19,
20]. In Refs.[
21,
22], several built-in self-testing techniques are proposed to detect the amplitude and phase behaviors of mmWave phased-array transceivers, and they are able to effectively improve the testing efficiency and make rapid calibration possible. Ref. [
10] reports a 39 GHz phased-array transceiver with built-in amplitude- and phase-calibration modules that alleviates the phase and amplitude mismatch of the transceiver channels. Nevertheless, these designs still suffer from certain detection/calibration deviations, complex circuit implementation, and large chip sizes.
To prominently increase the data rate and spectrum efficiency, many efforts have also been made in the architectures of the multi-stream beamforming front-ends. In addition to digital beamformers, the sub-array technique is popularly used for large-scale phased-array transceivers to achieve multi-beam operation[
23,
24]. The basic idea of the technique is to divide the antenna aperture of a phased array into several parts and form a certain number of beamformers; moreover, the number of beams and sub-array scale can be reconfigured to meet the different applications; however, this architecture requires complex control modules and sacrifices the gain of the antenna array. Dual-polarization phased-array transceivers have been also widely adopted in multi-beam systems; however, the beam number is usually limited to two[
27,
28]. Fullyconnected phased-array front-ends are proposed in Refs.[
6,
25,
26] which also feature multiple simultaneous beam formations, whereas the crossbar connection network is complicated and lossy and hence limits the overall array efficiency and scalability. In practice, phased-array-based mmWave systems also have disadvantages in terms of the time-consuming target searching and switching time between the base station (BS) and the user equipment (UE) which may be up to tens of milliseconds [
29]. To alleviate these problems, several multi-stream systems are proposed based on photonic-aided beamformers[
30,
31], such as the Rotman lens; nevertheless, they are difficult to implement in UE equipment since they are bulky in size and their performance is sensitive to mechanical vibration and temperature variation [
32]. Alternatively, a frequency-domain-multiplexing multi-input multi-output (MIMO) array with a single-wire interface is demonstrated in Ref. [
33], while it requires multiple local-oscillator (LO) signals to simultaneously process different intermediate-frequency (IF) signals.
A dynamic multi-beam architecture and corresponding CMOS transceiver chipset are introduced to address these technical challenges. As presented in Fig. 1(b), the entire system incorporates a multi-beam antenna array, multi-beam selector, and transceiver chains. Since the beamforming relies on the antenna array and beam selector and every transceiver chain can manipulate an independent beam, the architecture does not need an additional phase and amplitude calibration process to realize accurate beam direction. Besides, the presented architecture is more flexible in controlling the beam number compared with phased-array systems. Each transmitting (TX)/receiving (RX) chipset consists of two TX/RX frequency-conversion channels. Several circuit techniques for key building blocks in the transceiver chipset are also introduced to obtain good linearity performance. To increase the output power and power efficiency, a gallium–arsenide (GaAs) power amplifier (PA) is added to each TX chain. As a result, the proposed MIMO architecture can achieve large coverage. The antenna array and beam selector are realized by substrate-integrated-waveguide (SIW) structures; thus, they have compact sizes and can be implemented on printed circuit boards (PCBs). From Table 1, it can be seen that although the proposed one has penalties of the system assembly complexity and flexibility of beam scanning, compared with the phased-array architectures, it has advantages in terms of the front-end chip implementation, beam control, speed of beam switch, and spectral efficiency.
Fig. 1. System architectures for 5G NR. (a) Analog phase-shifting phased-array front-end; (b) proposed multi-beam MIMO front-end. IF: intermediate-frequency; PCB: printed circuit board; SIW: substrate-integrated-waveguide; TX: transmitting; RX: receiving; GaAs: gallium–arsenide; PA: power amplifier; N: number of the channel.
Table 1 Comparison of the phased-array and proposed dynamic multi-beam architectures.
For 5G mmWave applications, a high-performance package technology is also required. In this design, a low-temperature co-fired ceramic (LTCC) process, which presents low-loss dielectrics and reliable multilayer implementation [
34], is developed for the mmWave transceiver chipset. Although the LTCC processes have been widely used in the mmWave passive circuit and component designs[
35,
36], the loss and thermal performances of LTCCbased packaging for mmWave large-scale chips must be further explored. In this article, we analyzed the high-frequency characteristics of the key structures in the LTCC package, including striplines, vertical via transition, and bonding wires.
This article expands upon our earlier work [
37] and is organized as follows. Section 2 presents the system considerations and link budget analysis of the 39 GHz transceiver. Section 3 elaborates the circuit design of the transceiver. Section 4 introduces the LTCC-based package implementation. Section 5 illustrates the chip-level and system-in-package (SIP)-level measurement results and demonstrates the multi-beam prototype. Finally, this paper is concluded in Section 6.
2. Analysis and consideration of the system architecture
2.1. Link budget analysis
To facilitate circuit and system implementation, the link budget of the proposed 5G multi-beam architecture is analyzed. For the TX mode, the targeting effective isotropic radiation power (EIRP) is set as 50 dBm for moderate/long-distance wireless communication, and it can be calculated by
where
Pt,
GANT, and
LANT denote the output power of each TX channel, gain of the antenna array, and loss of the antenna’s feed line, respectively. Since the SIW-based multi-beam antenna arrays that will be used have a
GANT value of approximately 20 dBi and
LANT value of 2 dB in the mmWave regime[
38,
39],
Pt should reach 32 dBm to achieve the 50 dBm EIRP. However, this value is beyond the capability of a single PA in CMOS technology. Although the combination of multiple PAs can enlarge the output power, the power efficiency of the entire system will seriously deteriorate and the chip size will be too large [
40]. To tackle these issues, a GaAs PA, as illustrated in Fig. 1(b), will be adopted in each TX channel. It has a gain of around 35 dB and an output 1 dB compression point (OP
1dB) of about 34 dBm. Because of the GaAs PAs, the CMOS chip only needs to deliver 0 dBm linear power. Note that the interconnection lines between the CMOS chip and GaAs PA may lead to considerable loss, which is estimated to be 3 dB. Therefore, the OP
1dB of the CMOS TX channel is set as 5 dBm to ensure a certain power margin.
For the RX mode, the RX signal power (Pr) can be learned by
where
R and
represent the working distance and the wavelength of the radiated electromagnetic (EM) wave in the air.
is the path-loss factor. Based on Eq. (2), the theoretical
Pr ranges from –30 to –45 dBm for a 50–300 m operating distance when the EIRP of the transmitter is 50 dBm. The input 1 dB compression point (IP
1dB) per channel is thus chosen as –25 dBm to maintain a reasonable dynamic range and tolerate interference from other BSs. Based on the 3GPP release, the 39 GHz transceiver is required to support a 400 MHz signal bandwidth. To perform the 64-quadrature amplitude modulation (QAM) modulation, the error vector magnitude (EVM) should be lower than 8%, and the minimum corresponding signal-to-noise ratio (SNR
min) of the RX channel is 22 dB. For a targeting receiver sensitivity of –58 dBm, the noise figure (NF) of the RX link can be derived based on the given signal bandwidth and SNR
min [
41], which needs to be less than 8 dB. Considering an
LANT of 2 dB, the NF of the CMOS chip should be smaller than 6 dB. Since analog-to-digital converters in the baseband circuits need 7 dBm driving power, the gain of the CMOS RX channel is set as more than 47 dB. To meet the requirements of different application scenarios, the CMOS chip should also integrate gain-controlling blocks to control the output power of the transmitter and extend the dynamic range of the receiver. In this work, the gain-tuning range of each channel is set as 31 dB with a 1 dB gain-tuning step. Through the literature review and EM simulation, the mutual coupling among different beam ports of the used SIW-based beam selector is learned, which is less than –20 dB in the mmWave range. Therefore, the isolation between the two channels in the CMOS chip is set to be larger than 30 dB to avoid worsening the crosstalk of the entire system. The key system specifications of the CMOS chip are summarized and listed in Table 2.
Table 2 Key specifications of the CMOS chip for the 5G multi-beam MIMO system.
SNR: signal-to-noise ratio.
a Including 2 dB link margin
2.2. CMOS transceiver architecture
Besides the aforementioned requirements, several significant preconditions for CMOS chips should be addressed: ① high scalability for multi-beam MIMO applications; ② low complexity of interconnection between the CMOS chips and other modules in system boards; ③ proper input/output (I/O) interface design to minimize the performance degradation caused by system routing; ④ symmetrical layout and high channel isolation to ensure channel consistency; and ⑤ compact packaging for mmWave CMOS chips to mitigate the assembly difficulty and cost of large-scale MIMO systems.
To tackle the above technical challenges, an architecture for the CMOS chipset is proposed and shown in Fig. 2. Both the TX and RX chips consist of two channels, an LO chain, and a serial peripheral interface (SPI) module. Each TX channel is comprised of an IF mixer, RF mixer, five-bit attenuator, and PA; while the RX channel consists of a low noise amplifier (LNA), five-bit attenuator, RF mixer, IF mixer, and IF amplifier. To minimize LO leakage and improve image rejection, a superheterodyne topology is adopted in this work. As illustrated in Fig. 2, the frequency schemes of RF, internal IF, and external IF are set to 38.5, 11.5, and 2.5 GHz, respectively. The corresponding LO frequencies of the RF and IF mixers are 27 and 9 GHz, respectively. A 9 GHz sinewave signal from an off-chip module is injected into the chip to provide the LO signal for the IF mixer. Because the LO frequency of the RF mixer
is three times that of the IF mixer
, a injection-locked frequency tripler (ILFT) is employed to multiply the externally input LO signal and generate the RF mixer’s LO. Compared with the conventional architecture with an onchip phase-locked loop (PLL) [
42], the LO chain exploits the benefits of the simple circuit design and compact layout. Furthermore, based on the LO chain, the chipset is easy to assemble a larger MIMO system.
Fig. 2. Diagrams of the proposed TX and RX chips. (a) TX; (b) RX. ILFT: injection-locked frequency tripler; SPI: serial peripheral interface; LNA: low noise amplifier.
In practice, mmWave multi-channel transceivers based on CMOS technologies suffer from some disadvantages in terms of poor substrate isolation and layout-dependent parasitics. Therefore, fully differential structures are used to implement all the building blocks in the transceiver, which are robust to the severe parasitic effects of ground and supply lines as well as those of packages. Three baluns are employed in the RF and LO chains to convert the single-ended/differential signal into the differential/ single-ended form.
Fig. 3. (a) Schematic of the RF and IF up-conversion mixers; (b) simulated input impedance of the CS stage and CSCG stage. MR1–MR8: transistors in the schematic; LR1–LR6: inductors in the schematic; CR1–CR3: capacitors in the schematic; VDD: supply voltage; VmR: bias voltage of the transistors MR1 and MR4; VaR: bias voltage of the transistors MR2 and MR3; VgR: bias voltage of the transistors MR5–MR8; IFin+, IFin–: input IF signal; LOin+, LOin–: input LO signal; RFout+, RFout–: output RF signal; Zin: the input impedance; Zin_CS: the input impedance of the conventional Gilbert mixers; Zin_CSCG: the input impedance of the proposed topology.
In practice, mmWave multi-channel transceivers based on CMOS technologies suffer from some disadvantages in terms of poor substrate isolation and layout-dependent parasitics. Therefore, fully differential structures are used to implement all the building blocks in the transceiver, which are robust to the severe parasitic effects of ground and supply lines as well as those of packages. Three baluns are employed in the RF and LO chains to convert the single-ended/differential signal into the differential/ single-ended form.
3. Circuit implementation
3.1. Transmitter channel
As presented in Fig. 2(a), the TX channel adopts the superheterodyne architecture. To attain high linearity and LO isolation to deal with the large input IF signal and LO self-mixing, a double-balanced Gilbert topology with a linearity-enhancement technique is employed to design both the IF and RF upconversion mixers. As shown in Fig. 3(a), the transconductance (
gm) stage is composed of a common-source (CS) structure with source-degeneration inductors and a common-gate (CG) structure. The CS transistors M
R1 and M
R4 are biased in the saturation region, while the CG transistors M
R2 and M
R3 work in the weak inversion region. Under this bias condition, the third-order
gm of the CS transistors has the opposite polarity to that of the CG transistors. By optimizing the bias voltages and device sizes of the CS and CG structures, the summed third-order
gm of the two paths can be eliminated, which improves the linearity of the circuits [
43].
Due to the parasitic gate-to-source capacitor of MR1, the input impedance of the conventional Gilbert mixers (Zin_CS) encounters a large imaginary part and a sharp variation along with the operating frequency as illustrated in Fig. 3(b). This limits the input matching bandwidth. Extra components, such as large inductors, are required to deal with the large imaginary part of the input impedance, which will lead to some penalty of the chip area and loss. However, the input impedance of the proposed topology (Zin_CSCG) is determined by both the CS and CG paths’ input impedances. The simulated Zin_CSCG is also plotted in Fig. 3(b), whose imaginary part is much smaller and has flatter frequency response than that of Zin_CS. This finding indicates that the proposed topology can easily achieve wideband impedance matching with a previous stage or source impedance (50 Ω). The post-layout simulation shows that the up-conversion mixers achieve a gain of around 0 dB and –1 dBm IP1dB at 38.5 GHz while consuming 34.2 mW direct-current (DC) power.
The RF up-conversion mixer is followed by a five-bit attenuator as shown in Fig. 4(a). The 1, 2, and 4 dB attenuation cells are realized by a bridge-T topology, while the 8 and 16 dB attenuation cells adopt a
π-type topology. To reduce the phase variation during different states, a tail capacitor C
t1/C
t2 is introduced in the shunt branch of each attenuation cell [
44]. From Fig. 4(b), it can be observed that the phase response of the attenuation cell is sensitive to C
t1/C
t2. Therefore, the phase delay in the attenuation state will be compensated by C
t1/C
t2; hence, the phase difference between the attenuation and reference states can be effectively minimized. In this design, C
t1/C
t2s of the 1, 2, 4, 8, and 16 dB attenuation cells are 71, 27, 46, 30, and 34 fF, respectively. As illustrated in Fig. 4(b), the measured root-mean-square (RMS) phase error of the attenuator is lower than 3.8° across 37–41 GHz. In addition, a large resistor is added to the bulk nodes of the switches M
A1–A4 to prevent RF signal leakage from transistors’ channels to the ground, thereby decreasing the loss. As a result, the attenuator achieves an amplitude range of 31 dB with 7 dB loss.
Fig. 4. (a) Schematic of the attenuator; (b) simulated phase response of the 8 dB attenuation cell and measured RMS phase error of the attenuator. RMS: root-meansquare; BT: bridge-T; L1, L2, L4: series inductors for the inter-stage impedance matching; B1, B2, B5: logical controlling bits; Rs1, Rs2: the resistors in the series branches of the circuit; Ms1–Ms4: transistors in the circuit; Ro, Rp1, Rp2: the resistors in the parallel branches of the circuit; Ct1, Ct2: tail capacitors.
As presented in Fig. 5, the PA is realized by a two-stage differential three-stacked structure. The transistors are biased in class-AB mode to balance the linearity and power efficiency. By stacking three transistors, the supply voltage can be prominently improved without operating transistors beyond the breakdown voltage. The output power is also enhanced accordingly. Compact 1:1 transformers (TFP1 and BNP1) are employed to serve as the input and output matching networks. BNP1 also transfers the differential signal to the single-ended mode for the measurement and package requirements. In this design, the supply voltage for the PA is set as 1.8 V. It draws a 50 mA DC current and delivers a linear output power of 7.5 dBm at 38.5 GHz according to the post-layout simulation.
Fig. 5. Schematic of the PA. Vin+, Vin–: input differential signal; Vout: output singleended signal; VPo1+,VPo1–: output signal of the first stage; VPi2+, VPi2–: input signal of the second stage; TFP1: input transformer of the PA; kP1: coupling coefficient of TFP1; LP1: load inductors of the first stage; LP2: input-matching inductors of the second stage; CP1, CP2: capacitors in the PA; MP1–MP6: transistors in the PA; BNP1: output balun of the PA; kP2: coupling coefficient of BNP1.
3.2. Receiver channel
Similar to the TX channel, the RX channel also adopts a dualconversion architecture and is composed of an LNA, a five-bit attenuator, two down-conversion mixers, and an IF high-gain amplifier. The attenuator is same as that in the TX channel. To compensate for the attenuator’s loss and suppress the following stages’ noise contribution, a three-stage topology is used to implement a high-gain LNA, as shown in Fig. 6(a). The first stage is realized by a CG topology with a transformer-based
gm-boosting technique to achieve both the input impedance matching and noise matching, thus improving both the gain and noise performance. The second and third stages are based on a CS structure. Cross-coupled capacitors are used in the last two stages to neutralize parasitic gate-to-drain capacitors to obtain high gain. A transformer-based positive feedback network between the source and drain nodes of the transistors M
L2 is also employed to further reduce the noise contribution of the second stage and extend the inter-stage matching bandwidth [
45]. The stability performance is another critical challenge for the proposed LNA because it has a gain of more than 30 dB. Thanks to the capacitive neutralization technique and the feedback transformer in the second stage, the LNA has good stability in the differential mode. However, the undesired common-mode signal, which is caused by the imbalance of the balun and mismatch of the devices and interconnects, will be amplified by each stage of the LNA, which may lead to a risk of oscillating. As shown in Fig. 6(b), the simulated common-mode stability factor of the traditional structure is less than 1 across 31.5–34.6 GHz. To solve the problem, a transmission line (TL) is added to the common-mode point of the third stage to suppress the common-mode signal. As a result, the LNA achieves excellent stability in both the differential and common modes due to these methods (Fig. 6(b)). According to the circuit simulation, the LNA, which draws 48 mW DC power, attains a gain of 30.5 dB, NF of 3.9, and IP
1dB of –23 dBm at 38.5 GHz.
Fig. 6. (a) Schematic of the LNA; (b) post-layout simulated differential-mode and common-mode stability factors.Vout+, Vout–: output differential signal; Vin: input singleended signal; TL: transmission line; BN1: input balun; TFL1: transformer in the first stage of the LNA; kL1: coupling coefficient of TFL1; TFL2: transformer in the second stage of the LNA; kL2: coupling coefficient of TFL2; LL1, LL2: inductors in the schematic for impedance matching; ML1–ML3: transistors in the schematic of the LNA; CL1–CL5: capacitors in the schematic of the LNA.
Fig. 7(a) shows the topology of the IF and RF down-conversion mixers. The gm stage uses a CG structure for wideband impedance matching. To enlarge the gain, a transformer-based feedback technique is used between the source and drain nodes of the gm stage transistors MI1 and MI2. Fig. 7(b) depicts the physical structure of the differential transformer. In addition, the transformer reduces the coupling between the gm and switching stages, thus enhancing the LO-to-RF isolation. The RF down-conversion mixer consumes 10.5 mA current under 1.8 V supply voltage and achieves 7.3 dB gain and –5.9 dBm IP1dB at 38.5 GHz.
Fig. 7. (a) Schematic of the RF and IF down-conversion mixers; (b) implementation of the transformer feedback. VbiasI: gate bias voltage of the transconductance stage; RFin+, RFin–: input RF signal; IFout+, IFout–: output IF signal; PIB1, PIB2: positive-channel transistors in the output buffer of the mixer; MIB1, MIB2: negative-channel transistors in the output buffer of the mixer; RI: feedback resistors in the output buffer of the mixer; CI1–CI4: capacitors in the schematic; MI1–MI6: transistors in the mixer; LIdiff: differential load inductors in the mixer; LIP1, LIP2: drain inductors of the transconductance stage; LIS1, LIS2: source inductors of the transconductance stage; TFI: transformer in the mixer; kI: coupling coefficient of TFI.
As illustrated in Fig. 2(b), the IF mixer is followed by a fourstage IF amplifier. Fig. 8 shows the schematic of the circuit. The first three stages are realized by a CG structure with a currentsource load. To suppress the common-mode signal, a resistor RI1 is inserted between the common-mode path and ground in the first two stages. The final power stage uses the cascode structure with an inductive differential load to deliver high output power (Fig. 8). With a 1 V supply voltage, the cascode amplifier can also undergo a high voltage swing at the drain node. To conserve the chip size, the inductorless method is used to tandemly connect the amplification stages. The measurement results show that the IF amplifier has a 27 dB gain and 8 dBm OP1dB at 2.5 GHz with a power consumption of 37.4 mW.
Fig. 8. IF amplifier’s schematic. MA1–MA6: transistors in the IF amplifier; RAB: bias resistors; RA1: source-degeneration resistor in the first/second stage; CA1–CA3: capacitors in the circuit; LA1: load inductors of the IF amplifier; Vi2/3+, Vi2/3–: input signal of the third/fourth stage of the IF amplifier; Vo1/2+, Vo1/2–: output signal of the first/third stage of the IF amplifier; VAB1: gate bias voltages of the common-source transistors; VAB2: gate bias voltages of the common-gate transistors.
3.3. LO chain
The LO chain, as presented in Fig. 2, is used to provide the LO signals for both the IF and RF mixers in the two TX/RX channels. An external 9 GHz LO signal is input and transferred into the differential form by an on-chip balun. The balun is realized by using a 3:3 transformer with a coupling coefficient of 0.72 (Fig. 9(a)). Both the primary and secondary windings use the top metal to attain a high quality factor. The EM simulated phase error, amplitude mismatch, and loss are 0.5°, 0.25 dB, and 2.5 dB at 9 GHz, respectively. Then, the differential input signal is split into three parallel paths by a differential power divider to drive the two IF mixers and an ILFT. In addition, three identical IF buffers are added to the three parallel paths to compensate for the loss triggered by the balun and power divider, and they also provide a constant load impedance for the three paths of the power divider, thus minimizing the imbalance of LO power for the different channels. With the ILFT, the external input LO signal’s frequency is multiplied by three. The generated third-order harmonic signal is divided into two paths by a compact passive divider and amplified by two parallel RF buffers to drive the two RF mixers in the TX/RX chip. To save the chip area, the power divider is reused as the interstage matching networks, and their layouts are designed to be as symmetrical as possible to minimize inconsistencies in the LO input power to the two channels, as shown in Fig. 9(b). All the buffers in the LO chain are realized by a CS topology with a differential inductive load to obtain adequate gain and output power, as presented in Fig. 9(c).
Fig. 9(d) illustrates the schematic of the ILFT. For the injectionlocked oscillator, the locking range is dominated by the amplitude of the third-order harmonic injected into the oscillator [
46]. Therefore, the transistors M
T5 and M
T6 for harmonic generation are designed with a conduction angle of 100° for the maximum third harmonic component. Besides, the feedback resistors R
T1 and R
T2 are employed to further improve the locking range. The varactors C
T1 and C
T2 are adopted to compensate for the process, voltage, and temperature (PVT) variations. The measured locking range of the ILFT is from 8.40 to 9.66 GHz with an input power of 0 dBm and 4.6 mW DC power consumption. Fig. 9(e) shows the measured phase-noise performance. The phase noise of the output signal of 27 GHz at an offset of 1 MHz is –125.1 dBc, while that of the input signal of 9 GHz is –134.9 dBc. The phase-noise degradation is 9.8 dB, which is close to the theoretical value of 9.5 for frequency multipliers with a multiplication ratio of 3. Therefore, the ILFT has a small impact on the phase-noise performance of the LO signal for the transceiver.
Fig. 9. (a) 3D view of the LO input balun; (b) layout view of the RF passive divider with the buffers; (c) buffers’ topology; (d) schematic of the ILFT; (e) measured phase noise of the ILFT. VBB: gate bias voltage of the buffer; LB1: load inductors of the buffer; RBB: bias resistors of the buffer; MB1: transistors in the buffer; CB1, CB2: capacitors in the buffer; MT1–MT6: transistors in the ILFT; LT1, LT2: drain inductors in the ILFT; CT1, CT2: varactors in the ILFT; RT1, RT2: gate resistors in the ILFT; Vt: tuning voltage of the varactors.
3.4. Layout consideration
Thanks to the differential structures, the layouts of the mmWave circuits are designed symmetrically to minimize the effects of the parasitics of the ground and supply lines and hence maintain good RF performance. To minimize the layoutdependent effects and ensure good consistency of the channel response, layouts of the two TX/RX channels are also placed as symmetrically as possible. The LO chain and SPI module are inserted between the two TX/RX channels, which leads to equallength and symmetrical LO feeding structures for each channel (Fig. 9(b)). Due to the symmetrical layout, the LO chain provides equal driving power to the mixers in the two channels. It also guarantees considerably high channel isolation. In addition, metallic barriers that are stacked from the substrate to the top metal and connected to the ground plane, are utilized in each channel to further improve the channel isolation.
4. LTCC-based packaging design
Compared with conventional packaging processes, the LTCC package features higher reliability and relatively lower loss in mmWave bands. Therefore, it is adopted to package the 39 GHz transceiver chipset. Figs. 10(a) and (b) show the 3D and top views of the LTCC packaging. It consists of 18 layers of insulator substrate (Ferro A6 with a thickness of 92 μm and relative dielectric constant (εr) of 6.0) and 19 metal layers (silver with a thickness of 8 μm). Four ground planes (first layer, eighth layer, twelfth layer, and nineteenth layer) separate the package box into three functional regions: digital control (layers 2–7), RF signal stripline (layers 9– 11), and power supply (layer 13–18). These regions minimize the crosstalk among the different types of signals. The package size is approximately 9.000 mm × 9.000 mm × 1.826 mm.
A 3 mm × 3 mm cavity with a depth of 300 μm is excavated to place the chip; thus, the CMOS chip and top layer of the package have the same height. The structure shortens the length of the bonding wires from the chips to the package and mitigates the severe impact of bonding wires in the mmWave regime. The TX and RX chips are designed with similar layout frameworks. Therefore, they share the same package structure. Since the RF port locations of the TX chip are distinct from those of the RX chip, two extra RF signal striplines are added in the package, as shown in Fig. 10(b). This shared package can simplify the system assembly and decrease the packaging cost.
Fig. 10. Physical structure of the LTCC package. (a) 3D view; (b) simplified top view (only shows the signal paths). SMD: surface mounted device; IF1p, IF1n: the first IF I/O ports; IF2p, IF2n: the second IF I/O ports; RX_RF1/RX_RF2: RF input port of the first/second RX channel; TX_RF1/TX_RF2: RF output port of the first/second TX channel; L1: the first layer; L8: the eighth layer; L12: the twelfth layer; L19: the nineteenth layer.
4.1. Signal stripline and vertical via transition design
Fig. 11(a) shows the RF signal transmission structure. It is comprised of a coplanar waveguide (CPW) bonding finger, vertical via transition I, RF stripline, vertical via transition II, and CPW surface mounted device (SMD) pin. The stripline is implemented on the tenth layer, while the ground planes are implemented on the eighth and twelfth layers. The upper and lower symmetrical ground surfaces lead to uniform electric field distribution and provide an effective EM shield [
47]. In addition, two rows of ground vias on both sides of each stripline are used to further reduce the EM dispersion and radiation. Therefore, the loss of the stripline will be reduced, and the interference from other striplines can be isolated.
Fig. 11. (a) Cross-sectional view of the RF signal transmission path; (b) vertical via transition. CPW: coplanar waveguide.
Two rows of ground vias are also employed around the vertical via transitions which are used for interconnections between the CPW line and stripline. To investigate their characteristics, an EM simulation is conducted for the vertical via transition I. As depicted in Fig. 11(b), the height and diameter of the vertical vias are 901 and 100 μm, respectively. Fig. 12 presents the top view of the simulated electric-field distributions around the vertical via transition with different numbers of ground vias. It can be seen that the electric field is constrained more strictly inside the vias along with the increase in the number of ground vias. The EM simulation result shows that the losses of transition with 2, 4, 8, and 20 ground vias are around 0.200, 0.120, 0.100, and 0.095 dB at 39 GHz, respectively. The EM coupling effect among adjacent channels’ transitions, which is shown in Fig. 13, is also studied. The simulated EM coupling between Port 1 and Port 4 is –64.0 dB with a circle of ground vias, while that is –85.7 dB with two circles of ground vias. Therefore, the ground vias not only can reduce the loss but also mitigate the crosstalk among the adjacent channels. In this design, two circles with a total of 20 ground vias are adopted to implement the vertical via transition to balance the RF performance and package size.
Fig. 12. Electric-field distribution versus the number (2, 4, 8, 20) of ground vias.
Fig. 13. Coupling model between two vertical via transitions of adjacent channels.
4.2. Bonding-wire transition
The bonding-wire transition is another pivotal component in the mmWave package. Although the cavity is used to shorten the lengths of bonding wires, the wires still have a considerable impact on the entire performance of the system, particularly those at RF terminals. Fig. 14(a) shows the 3D view of a bonding-wire transition between the ground-signal-ground (GSG) pads and CPW bonding finger. Fig. 14(b) depicts the physical structure of the golden bonding wires, which have a diameter, length, and height of 25, 250, and 100 μm, respectively. To ensure the simulation accuracy, the packaging model for EM simulation includes all the bonding wires and signal transmission structures. Fig. 15 displays the EM simulated reflection coefficients of the port looking into the SMD pin and the losses with different numbers of bonding wires at an RF terminal. The trough of the reflection coefficient moves to a higher frequency, and the loss decreases when the number of the bonding wires increases. Because the equivalent inductance and parasitic resistance will proportionally decrease as the parallel bonding wires increase. However, the size of the pad limits the number of accommodatable bonding wires. In this design, we used three bonding wires at each RF pad to maintain good RF performance and impedance matching, while the DC and ground pads only use one bonding wire to reduce costs.
Fig. 14. (a) Bonding-wire transition between the GSG pads and CPW bonding finger; (b) physical structure of the golden bonding wire. GSG: ground-signalground.
Fig. 15. Simulated reflection coefficient and loss with the different numbers of the bonding wires.
5. System measurements and discussion
The 39 GHz two-channel transceiver chipset is fabricated in a standard 65 nm CMOS process and mounted in the LTCC package. The die photos and testing boards are shown in Fig. 16. The TX chip size is 2.4 mm × 2.8 mm, while the area of the RX chip is 2.8 mm × 2.8 mm. The TX and RX chips share the same LTCC package which is approximately 9 mm × 9 mm. The transceiver chipset is subjected to chip-level measurement and SIP-level measurement. Based on the designed chipset, a 39 GHz multi-beam MIMO prototype is developed for 5G NR. The OTA testing of the TX-to-RX communication link is also conducted to demonstrate the functionality of the 5G NR systems.
Fig. 16. (a) Die photo of the TX chip; (b) die photo of the RX chip; (c) test board of the TX front-end system in the LTCC package; (d) test board of the RX front-end system in the LTCC package. Reproduced from Ref. [
37] with permission.
5.1. Chip-level and SIP-level measurements
The chip-level and SIP-level measurement setups are shown in Figs. 17(a) and (b), respectively. The chip-level measurement for the gain and linearity performances is performed by a vector network analyzer (VNA). All DC, SPI I/O, IF, and LO pads are connected to PCB traces by golden bonding wires. An off-chip IF balun is used to convert the differential IF signal into the single-ended mode for measurement. An automatic testing system is also developed to capture the SIP-level performance.
Fig. 17. Measurement setups. (a) On-chip testing; (b) SIP-level testing; (c) testing of the single-channel TX-to-RX wireless link. FPGA: field-programmable gate array; SMA: small A type; GPIB: general-purpose interface bus; BW: bandwidth.
Fig. 18 shows the simulated and measured RF-port impedancematching characteristics of the TX and RX chips. The reflection coefficient at RF ports of the RX chip is lower than –10 dB across 36.3–42.0 GHz, while that of the TX chip is about –6 dB in the targeting band. The reason for the relatively poor impedance matching of the TX chip is that the reflection coefficient of the PA is sacrificed to improve the output power and power efficiency. Due to the relatively poor output matching, an interaction occurs between the CMOS TX chip and GaAs PA, and the gain and output power of the TX system deteriorate to some extent. However, the CMOS TX’s OP1dB has a nearly 2 dBm margin, and we can adjust the attenuator and input signal power to compensate for the loss. The SIP-level simulation and measurement are also presented in Fig. 18, and they take PCB transmission lines and 2.92 mm connectors into account. It can be observed that the SIP-level measured reflection coefficients agree well with the chip-level reflection coefficients, which indicates that the package-related degradation of the RF performance is significantly mitigated.
Fig. 18. Measured and simulated reflection coefficients with and without the package. (a) TX; (b) RX.
The measured conversion gains of the TX and RX channels with the LTCC package are presented in Figs. 19(a) and (b), and they are approximately 52.2 and 11.3 dB at 38.5 GHz, respectively. The losses of the IF balun and connectors are de-embedded in the testing. From Fig. 19, it can also be seen that the achieved RF bandwidths of the TX/RX chips are larger than 2 GHz. For multichannel on-chip systems, channel isolation is another critical specification. Therefore, the channel isolations of the TX and RX front-end systems in the package are measured and presented in Fig. 19. Benefiting from the fully symmetrical layouts of the chips and package used, the RX system’s channel isolation is better than 51 dB across 37–40 GHz, while that of the TX system is higher than 60 dB. The 32 measured gain stages of the TX SIP and RX SIP versus IF frequency are plotted in Figs. 20(a) and (b). The measured gain variation range is about 33 dB, which is slightly larger than the expected value of 31 dB. The main reason is that the attenuation cells are sensitive to the impedance of the adjacent cells and stages, especially the 8 and 16 dB attenuation cells. Besides, the deviation of the EM simulation for passive structures may also cause the scale-up of the gain-tuning range. Accordingly, the measured RMS gain errors of the transceiver are worse than the simulated results of the attenuator. As presented in Fig. 20(c), they are 2.8 dB in the TX chip and 1.3 dB in the RX chip.
Fig. 19. Measured maximum gain and channel isolation of (a) TX SIP and (b) RX SIP.
Fig. 20. Measured 32 Gain states. (a) TX SIP; (b) RX SIP; (c) RMS gain errors of the TX SIP and RX SIP.
Fig. 21(a) shows the measured OP1dB and saturated output power (PSat) of the TX SIP, which are 5.4 and 10.0 dBm at 38.5 GHz, respectively. Compared with the post-layout simulation results of the PA, the tested linearity of the TX deteriorates by approximately 2 dBm. The probable reason is that the chip’s operating temperature is higher than the one set in the simulation environment of the circuit simulation software. The other reason may be that the output matching balun’s loss is worse than the EM simulated loss. Within the frequency band of 37–40 GHz, the PSat of the TX channel is more than 8.4 dBm. The measured OP1dB and NF of the RX SIP are shown in Fig. 21(b). In the maximum gain state, the RX obtains an OP1dB of more than 7.2 dBm and an NF of less than 5.4 dB across 37–40 GHz. When the RX SIP operates in the minimum gain state, the IP1dB is better than –23 dBm. Thus, the RX chip achieves the targeting specifications that were introduced in Section 2. Fig. 22 depict the measured output power and LO leakage power of the TX/RX SIP, which are tested when the IF, LO, and RF frequencies are set to 2.5, 9.0, and 38.5 GHz, respectively. Note that the main spurs in the TX SIP are the 3LO component leaking from the LO to RF ports of the RF mixer and 3LO + LO component generated by the mixture of the RF mixer’s LO signal and IF mixer’s LO leakage, while those in the RX SIP are the LO component leaking from the LO to IF ports of the IF mixer and 3LO –LO component caused by the mixture of the IF mixer’s LO signal and RF mixer’s LO leakage. When the LO input power is 5 dBm, the measured spurious suppression of the TX SIP is more than 32 dB (Fig. 22(a)) while that of the RX SIP is more than 22 dB over the targeting frequency band (Fig. 22(b)).
Fig. 21. (a) Measured OP1dB and PSat of the TX SIP; (b) measured NF and OP1dB of the RX SIP.
Fig. 22. Tested output power and LO components leakage power. (a) TX SIP; (b) RX SIP.
5.2. Wireless communication link measurement
As shown in Fig. 17(c), a single-channel TX-to-RX communication link set up with two antenna modules whose gain is 20 dBi. The TX-to-RX distance is 1 m. A wireless connectivity tester is used to evaluate the EVM performance. The input IF signal is based on IEEE 802.11ac standard, and its bandwidth is 20 MHz, with a carrier of 2.25 GHz (limited by the used equipment). Fig. 23 shows the spectra and constellations of the received signal. Under the peak input signal power of –2.3 dBm for the TX channels, the tested singlechannel TX-to-RX EVM and spectral efficiency are 3.72 % and 3.25 bit·s–1 ·Hz–1 with 64-QAM modulation, respectively. With 256- QAM modulation, the demo is also tested and achieves an EVM of 3.76 % and spectral efficiency of 3.90 bit·s–1 ·Hz–1 .
Fig. 23. Measured constellation, spectral efficiency, and TX-to-RX EVM. Reproduced from Ref. [
37] with permission.
5.3. 39 GHz multi-beam MIMO prototype
Using the CMOS transceiver chipset, a 39 GHz MIMO prototype is developed [
48], as illustrated in Fig. 24. It adopts the dynamic multi-beam architecture shown in Fig. 2(b). The prototype includes four CMOS TX chips and four RX chips; thus, it has eight TX channels and eight RX channels and can support eight independent beams for MIMO operation. The beamformer is designed by a SIW-based Rotman lens and SIW-based slot antenna array with a 20 dBi gain. The measurement results show that each TX channel achieves an EIRP of more than 52 dBm at the OP
1dB, while the NF of the RX channel is less than 7.6 dB across 37–40 GHz.
Fig. 24. 39 GHz multi-beam MIMO prototype. Reproduced from Ref. [
48] with permission.
Online outdoor communication links for one-stream (1S) and two-stream (2S) transmission to single-user equipment (SUE) are demonstrated to evaluate the overall performance of the 39 GHz MIMO system. Fig. 25(a) presents the measurement setup of the outdoor wireless communication. The working distance ranges from 5 to 150 m. This OTA communication link is based on the communication of two sets of access point equipment (APE). The IF signal also adopts IEEE 802.11ac standard and has bandwidth of 80 MHz. The measured downlink throughput of 1S and 2S with different modulation schemes are illustrated in Fig. 25(b). The downlink throughputs of 1S transmission at 5, 50, 100, and 150 m are 185, 150, 130, and 90 megabits per second (Mbps), respectively. To meet the EIRP and linearity requirements for the different working distances, the attenuators are employed to tune the output power and calibrate the gain error of the TX channels and increase the dynamic range of the RX channels. Due to the good EVM performance of the CMOS TX/RX, the proposed MIMO system still can support 16-QAM (modulation and coding scheme 3) modulation at a 150 m distance. In the 2S transmission, the tested throughput of the prototype is almost twice as large as that of the 1S transmission (Fig. 25(b)), and hence the proposed architecture is feasible for multi-beam applications in the mmWave regime.
Fig. 25. (a) OTA measurement setup for the 5G MIMO prototype; (b) measured downlink throughputs and modulation scheme over 5–150 m. MCS: modulation and coding scheme; 1U1S: one user with one stream signal; 1U2S: one user with two streams signal. Mbps: megabits per second. Reproduced from Ref. [
48] with permission.
The overall performances of the front-end chipset are summarized and compared with state-of-the-art 5G mmWave transceivers in Table 3 [10,11,26,33,49,50]. Owing to the above techniques, the transceiver chipset attains the largest gain range of 33 dB and excellent NF and linearity with comparable power consumption, compared with the other works in Table 3.
Table 3 Performance summary and comparison with the state-of-art 5G mmWave transceivers.
6. Conclusions
In this article, a 39 GHz transceiver chipset is proposed and demonstrated for 5G mmWave applications. Each TX/RX chip integrates two variable-gain frequency-conversion channels and can support two simultaneous independent beams. Several layout considerations and circuit techniques are introduced to improve the overall performance of the mmWave front-end system. Furthermore, a TX and RX shared LTCC package with excellent RF performance is developed for the 39 GHz chipset. The TX-to-RX wireless communication link measurement characteristics show that the proposed 39 GHz transceiver chipset can support even 256-QAM modulation transmission. A 39 GHz multi-beam MIMO prototype is also developed based on the CMOS transceiver chipset. OTA communication testing indicates that the prototype successfully achieves MIMO operation over 5–150 m distance. Therefore, the proposed CMOS transceiver and dynamic multi-beam architecture are feasible for mmWave MIMO applications. This article provides a potential solution for 5G mmWave communication.
Acknowledgments
This work was supported in part by National Natural Science Foundation of China (62171102 and 61931007), and in part by National Key Research and Development Program of China (2020YFB1805003).
Compliance with ethics guidelines
Yiming Yu, Zhilin Chen, Chenxi Zhao, Huihua, Liu, Yunqiu Wu, Wen-Yan Yin, and Kai Kang declare that they have no conflict of interest or financial conflicts to disclose.
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