Micro-electromechanical system (MEMS) micro force sensors are efficient and necessary tools in many biomedical studies. Such tools have been used to measure the Young’s modulus[1–2], viscosity[3–4], and locomotion traction [5] in living cells or tissues in order to study biological processes and biomedical reactions. Micro force sensors can provide precise force feedback in micro-robotic biomedical manipulations to improve the automation extent[6–7] and the survival rate of biological objects[8–9]. Recent studies have focused on the organelle or molecular level, thereby increasing the demand for ultralow force sensing below the nanonewton level. Current force-sensing devices are mainly based on sensing principles, such as capacitive[10,11], piezoresistive[12,13], and piezoelectric[14,15] principles. The movable gate field-effect transistor (MGFET) force sensor exhibits several advantages over its competitors, such as a high sensitivity derived from the transistor array design[16,17], convenient signal amplification, and modulation with integrated circuits [18], thus making the on-chip measurement of low-scale forces feasible. Compared with traditional metal-oxide semiconductor field-effect transistors, MGFET devices have a floating gate over the substrate channel area and can move along three axes due to the air gap, as shown in Fig. 1. The current between the source and the drain electrodes reflects the applied external loads. In terms of the gate moving direction, MGFET devices are divided into two types: vertically MGFETs (VMGFETs) and laterally MGFETs (LMGFETs). VMGFETs exhibit high sensitivity, while their movement range is limited by the small air gap thickness. Their measurement linearity deteriorates with an increase in gate vertical deformation. Unexpected rapidly increased loads usually occur during biomedical measurements, such as during membrane penetration in biological cell microinjections[19,20], when the force amplitude increases sharply and may exceed the measurement range of a VMGFET device. In LMGFETs, the gate moves laterally along the channel width, and the air gap remains constant. The measurement range of LMGFETs is larger than that of VMGFETs, and their output current changes linearly during the measurement range. Therefore, a highly sensitive LMGFET force sensor is more versatile than a VMGFET in biomedical measurement.

Fig. 1. Sensing unit of the MGFET. T_insu: insulator thickness; L_ch: channel length; Z_air: air gap thickness; W_ch: whole channel width.

Researchers have developed several MGFET devices on the basis of these two types, such as VMGFET-based accelerometers[21,22], differential amplifiers [23], and LMGFET-based displacement sensors [24]. Existing studies have found that the measuring sensitivity can be improved by scaling down the transistor size. However, the widely adopted long-channel model in Refs.[21–24], which ignores many scale effects, is inaccurate for describing MGFET performance, especially for devices with a small size. In our previous work, we proposed an accurate electrical model for small-scale VMGFET devices [25]. However, the movable gate of an LMGFET device partially covers the channel area, leaving the other part exposed. The operation behavior of LMGFET devices is relatively more complex than that of VMGFET devices, such that the previous VMGFET model is no longer applicable in LMGFET design. Therefore, a new precise electrical model is essential for the performance evaluation of small LMGFET devices. Moreover, the output current of an MGFET changes as its gate moves laterally and vertically, and loads from non-operation directions can produce considerable interference of output signals.

A differential sensing configuration has usually been adopted to attenuate the cross-axis coupling effect in MGFET devices[23,25]. However, this method is invalid for LMGFETs because the output current changes significantly when the gate moves vertically. The output change from lateral loads can be overwhelmed by vertical disturbances, producing undesirable measurement errors. Therefore, a novel decoupling movable structure and sensing configuration is required to improve sensing accuracy. The measuring sensitivity of MGFET devices can be further improved by lowering the stiffness of movable structures. In existing MGFET devices, movable structures are made of rigid materials, such as silicon [21] and nickel[22,24] with large stiffness, such that the movable structure can hardly deform. One feasible method to improve the measuring sensitivity is to replace these stiff materials with other flexible alternatives. However, this is difficult for LMGFET devices, as they require high-aspect-ratio structures, and no such attempts have been conducted before.

The main contributions of this work are as follows. First, a separated channel-based electrical model is proposed to describe the operation behavior of small LMGFET devices, and its improved accuracy and capability for performance evaluation are demonstrated. Second, the electrical and structural parameters of LMGFET devices are fully analyzed to optimize the performance of ultralow force-sensing applications. Third, a flexible sandwich structure is proposed for the LMGFET micro force sensor, which consists of a gold cross-axis decoupling gate array layer and two soft photoresistive SU-8 layers. The sensor utilizes a novel dual-differential decoupling sensing configuration that exhibits excellent sensing sensitivity and anti-interference capability. Finally, the proposed LMGFET force sensor is simulated with a practicable fabrication process. The proposed sensor breaks through the limitation between the sensing accuracy and measurement range of MGFET devices. Its measuring sensitivity is 4.65 μA·nN^–1 for a large measurement range of ±5.10 μN, and its nonlinearity is less than 0.78%. 

The rest of this paper is organized as follows: Section 2 models and analyzes the electrical behavior of the LMGFET. Section 3 illustrates the proposed LMGFET force sensor and describes the mechanical model and sensing configuration. Section 4 presents a practicable fabrication process for the proposed sensor. The theoretical model is then validated through simulation and experimental results, followed by a discussion of the sensor performance. Section 5 provides the conclusions.

 When the gate of an LMGFET moves laterally, the channel width changes such that the LMGFET can be divided into two separated parts—namely, a covered channel area with width W_chc and an uncovered channel area with width W_chu (W_chu = W_ch – W_chc) (where W_ch is the whole channel width). The two parts share some common parameters, such as the channel length L_ch, voltage difference between the gate and source electrode V_gs, and voltage difference between the drain and source electrode V_ds. Due to the difference in the gate modulation effect at different lateral positions, the electron conductance in each channel area differs significantly. The whole channel exhibits several individual electrical parameters, such as the gate capacitance C'_eff , carrier mobility U'_eff , and channel current I_ds. Thus, an investigation of the electrical parameters in each part is necessary in order to understand the operation principles of the LMGFET. Such an investigation is conducted in this section.

The capacitance between the gate and the covered and uncovered channel area changes when the gate moves laterally. Gate capacitance is a parameter describing the capacitance over a unit area. More specifically, the effective gate capacitance in the covered channel area C'_effc is the series capacitance of the air gap and gate insulator, which can be expressed as follows:

where ε₀ = 8.854 × 10^–14 F·cm^–1 is the permittivity of air; ε_insu is the permittivity of the insulator; Z_air is the air gap thickness; T_insu is the insulator thickness; and Z'_effc is the effective gate gap thickness in the covered area. A previous study assumed that the effective gate capacitance in the uncovered channel area C'_effu is constant during gate movement [24]; however, this assumption is not in accordance with reality and can cause many artifacts in the device performance estimation. In this study, we propose an accurate variable expression of C'_effu based on the fringe parasitic effect of the gate sidewall and bottom line[26,27]:   

where  is the effective gate thickness for the sidewall parasitic capacitance; T_g is the gate thickness; k and β are fitting parameters; and Z'_effu is the effective gate gap thickness in the uncovered area. 

The effective gate capacitance of the two separated areas is examined at different lateral and height positions and compared with simulation results from the finite-element method (FEM) software Ansoft Maxwell. In this calculation, the whole channel width W_ch is 20 μm; the air gap thickness Z_air is from 0.1 to 0.5 μm; the gate thickness T_g is 0.2 μm; the gate insulator is silicon nitride, and its thickness T_insu is 100 nm; and the channel length L_ch is 5 μm. During gate movement, most of the electric potential is concentrated in the covered area, and a small amount is scattered on the boundary edge because of the fringe parasitic effect. The effective gate capacitance in the covered channel area C'_effc remains almost constant at full width. As the covered area width W_chc approaches zero, the scattered potential proportion increases, and C'_effc experiences a small increase, as shown by the dots in Fig. 2. However, the relative error of C'_effc between the model and the simulation results is less than 3.0% for a small W_chc of 1 μm in three different air gaps. The value of the effective gate capacitance in the uncovered channel area C' _effu is one order less than that of C'_effc. The gate capacitance in the uncovered area mainly results from the scattered electric potential in the gate sidewall and bottom line. The total electrical potential remains constant, but the size of the uncovered area changes during gate movement. C' _effu exhibits an inversely proportional relationship with width in the covered area W_chc. When W_chc is low, C' _effu increases slowly because the change in W_chu is insignificant. However, the size of the uncovered area changes greatly as W_chc approaches the whole channel width, resulting in a rapid increase of C' _effu. The scattered electrical potential increases as the air gap Z_air decreases and then aggravates this phenomenon. The calculation of C' _effu also shows an excellent coincidence with the simulated results, where the largest relative error is less than 3.5%.     

Fig. 2. Relationship between the effective gate capacitances C'_effc and C' _effu, and the channel width at different air gaps. Lines represent the calculated capacitance, while scatters are the simulated results.

Threshold voltage is a crucial switch parameter modulating the current channel between the source and drain electrodes. The channel current exists only if the gate voltage is larger than the threshold voltage for an accumulation-type MGFET. For a depletion-type device, in which the channel current is originally induced, a gate voltage approaching the threshold value can break off the conducting channel. The covered and uncovered channel areas have different threshold voltages, so they can have different channel statuses during lateral and vertical gate movement. Considering the short and narrow channel effects, the threshold voltages in the two areas are modeled separately, as follows:

where is the work function difference between the gate and channel; is the channel built-in voltage, which is  and  for an N-channel device and a P-channel device, respectively; N_a/d is the net concentration of ionized acceptors in a P-type substrate and donors in an N-type substrate, respectively; q = 1.6 × 10¹⁹ C is the magnitude of the electron or hole charge, n_i is the intrinsic doping concentration of silicon, k_B is the Boltzmann constant, and T is the thermodynamic temperature; ε_si is the permittivity of silicon; V_bs is the voltage difference between the source and substrate electrodes; Q'_eff is the effective charge density of the channel, where the minus and plus signs are respectively for N-channel and P-channel devices; and F_S is the channel length coefficient, which is expressed as follows: 

where X_j is the depth of the PAN junctions in the source or the drain electrode; and , d₀, d₁, and d₂ are model parameters. F_Nc and F_Nu are the channel width coefficients in the covered and uncovered channel areas, respectively, and are expressed as follows:

where δ is the channel width model factor. The positive sign before the F_S term is for an N-channel device while negative sign is for a Pchannel device. The sign before the Q'_eff term is opposite compared with that before the F_S term, and the difference between the F_S and the Q'_eff term can primarily determine the value of the threshold voltage. For example, a large Q'_eff term can result in a negative threshold voltage for a depletion-type MGFET device with a Ptype substrate (Fig. 3).

Fig. 3. Relationship between the threshold voltages V_thc and V_thu, and electrical parameters at different width positions. (a) Net concentration of ionized acceptors in the substrate N_a; (b) effective channel charge density Q'_eff . Symbol lines indicate the threshold voltage in the covered channel area V_thc, and dotted lines indicate the threshold voltage in the covered channel area V_thu. Case_1–Case_4: N_a increases from 5 × 10¹⁴ to 5 × 10¹⁵ cm^–3 , while Q'_eff is kept low at 2.5 × 10⁸ C·cm^–2 ; Case_5–Case_8: Q'_eff increases from 1 × 10⁸ to 3 × 10⁷ C·cm^–2 , while N_a is kept at 1 × 10¹⁵ cm^–3 .

Although the channel length coefficient F_S remains constant, the channel width coefficient changes during lateral and vertical gate movements, especially for the uncovered channel area, whose effective gate gap Z'_effu varies significantly at different positions. Therefore, the threshold voltage will exhibit different characteristics in the two channel areas and needs comprehensive analysis. The effective charge density of the channel Q'_eff and the substrate concentration N_a/d are studied first. A P-type substrate device is adopted as an example, with the following parameters: The channel width W_ch is 20 μm, the air gap Z_air is 0.25 μm, the channel length L_ch is 5 μm, the P–N junction depth X_j is 0.5 μm, the intrinsic doping concentration n_i is 1.5 × 10¹⁰ cm^–3 , the implanted model constant = 0.04, d₀ = 0.0631353, d₁ = 0.8013292, d₂ = 0.01110777, the work function voltage difference φ_MS = 3.83 V, and the voltage difference between the substrate and the source electrode V_bs = 0 V. The remaining parameters are the same as those given in Section 2.1. The effect of the substrate acceptor concentration N_a is investigated from Case_1 to Case_4 in Table 1, where N_a increases from 5 × 10¹⁴ to 5 × 10¹⁵ cm^–3 , while Q'_eff is kept low at 2.5 × 10^–8 C·cm^–2 . For a small N_a in Case_1, both parts behave as depletion-type transistors, and the channel is initially conductive because their energy band has been bent by dominant electrons in the channel surface. To break off the conducting channel, a negative threshold voltage is required to attract holes in the substrate. However, V_thc becomes positive while V_thu remains negative when N_a increases to 1.0 × 10¹⁵ cm^–3 ; the covered part becomes an accumulation-type transistor, and the uncovered part remains a depletion type in Case_2. Because of its flat energy band, the channel in the covered area is not conductive until the inversion layer is formed, wherein holes gather in the channel surface under electrical potential forces resulting from a positive threshold voltage V_thc. This condition appears to be desirable for device design, because the uncovered part with a nonlinear effective gate capacitance can be eliminated. However, it results in poor device performance, as only the covered part contributes to the output current.

Table 1 Threshold voltage of covered/uncovered channel area under different electrical parameters.

^a ‘‘+” and ‘‘” refer to accumulation and depletion types, respectively.

^b ‘‘/+” indicates that the device changes from a depletion to accumulation type.

During LMGFET operation, V_thc decreases moderately and V_thu increases sharply as W_chc increases, indicating that V_thu is more susceptible to channel width modulation. More specifically, V_thu changes from –0.817 V at a W_chc of 13 μm to 0.074 V at a W_chc of 14 μm in Case_3. This condition can make the uncovered area change from a depletion type to an accumulation type during operation and should be avoided. When N_a increases above 5 × 10¹⁵ cm^–3 , the two areas become accumulation types in Case_4. The effect of the channel’s effective charge density Q'_eff is then investigated from Case_5 to Case_8, where Q'_eff increases from 1 × 10^–8 to 3 × 10^–7 C·cm^–2 . In these cases, N_a is kept at 5 × 10^–15 cm^–3 , a value that is commonly available using commercial silicon wafers. For a low Q'_eff of 1 × 10^–8 C·cm^–2 in Case_5, the covered part behaves as an accumulation-type transistor, while the uncovered part is a depletion type. Holes become dominant as Q'_eff increases above 5 × 10^–8 C·cm^–2 , allowing both areas to function as depletion-type transistors. 

The relationship between the threshold voltage V_th and the geometry parameters L_ch and Z_air is shown in Fig. 4, where N_a and Q'_eff are set at 1 × 10¹⁴ cm^–3 and 2.5 × 10^–7 C·cm^–2 , respectively. V_thc has a strong negative correlation with the air gap Z_air as the effective gate height Z' _effc increases. However, V_thc rarely changes for different channel lengths L_ch. V_thu increases slowly with an increase in channel length L_ch, but decreases significantly with an increase in the air gap Z_air for the same reason as V_thc. Therefore, the desired working types are achievable through appropriate assignment of electrical and geometry parameters. A nonzero gate voltage inducing a conducting channel in an accumulation-type device can probably produce an electrostatic force between the movable gate and substrate, resulting in undesirable vertical interference during operation [28]. The channel of a depletion-type device is conducted, although the potential difference is zero. Thus, electrostatic forces are eliminated. In other words, a depletion type is strongly expected for LMGFET devices. Therefore, the following design analysis is based on the norm that an LMGFET is free from electrostatic forces with a fixed gate voltage of 0 V. 

Fig. 4. Relationship between the threshold voltage V_th and the geometry parameters L_ch and Z_air at different width positions.

The surface current density in two channel areas differs from each other. Thus, the current between the drain and source electrode in each area should be calculated individually, and the total output current should be their sum. By integrating the density of the channel surface carriers between two electrodes [29], the output current in the covered area I_dsc and the output current in the uncovered area I_dsu are defined as follows: 

where  is a voltage modulation coefficient in the covered and uncovered areas; μ'_effc and μ'_effu are the effective carrier mobilities in the covered and uncovered areas, respectively, which can be expressed as follows: 

where μ₀ is the surface mobility of the carriers at a low electric field; δ is the vertical potential field factor; and V_max is the saturated velocity of the carriers. Effective carrier mobility is mainly regulated by the term , which accounts for the vertical potential degrading effect, and by the term , which describes the velocity limitation and lateral potential degrading effect [30]. μ'_effc and μ'_effu change when the gate shifts to different channel widths and heights. I_ds approaches the value of the saturated current I_dsat when V_ds increases to a saturated status. 

As discussed in our previous work [25], the saturated voltage of small-scale devices results from a saturated velocity. The saturated voltages in the covered area V_dsatc and in the uncovered channel area V_dsatu are expressed as follows: 

where I_dsat is the maximum controllable output for LMGFET devices and is directly affected by the threshold voltage applied at the drain electrode. Fig. 5 illustrates the relationship between the threshold voltage in the two areas and the electrical parameters (with acceptor concentration N_a and effective channel charge density Q' _eff) and geometrical parameters (with air gap Z_air and channel length L_ch). Aside from the similar parameters in the last calculation, the voltage difference between the substrate and source electrode V_gs is 0 V, the carrier surface mobility μ₀ is 700 cm² ·V^–1 ·s^–1 [31], and the saturated velocity V^max is 8 × 10⁶ cm·s^–1 [32]. The saturated voltages of the two areas decrease with an increase in N_a and Q'_eff; they also decrease with a decrease in the corresponding channel width (W_chc/W_chu). More specifically, the decreasing amplitude due to a small width becomes distinct with an increase in N_a and Q'_eff . The green lines in Fig. 5(a) correspond to Case_2 in Table 1. The covered channel area is currently broken off, so the saturated voltage in the covered area is 0. The geometric parameters exhibit an opposite influence to the electrical ones. V_dsatc increases with an increase in L_ch and Z_air, as shown in Fig. 5(b). V_dsatu increases with an increase in L_ch and is insensitive to the change in the air gap Z_air. For a channel width W_chu of 10 μm, V_dsatu only changes by 0.18 V when Z_air changes from 0.1 to 0.5 μm. 

Fig. 5. Relationship between the saturated voltages V_dsc and V_dsu, and the electrical parameters and geometry parameters at different width positions. (a) Doped concentration of substrate N_a with effective channel charge density Q'_eff; (b) channel length L_ch and air gap Z_air. L_ch is 5 lm and Zair is 0.25 μm for (a), while Q'_eff is 2.5 × 10^–8 C·cm^–2 and N_a is 1 × 10¹⁵ cm^–3 for (b).

 The adopted saturated voltage is set to the lowest value during the gate’s lateral movement to analyze the saturated current. The current I_ds is assumed to be constant if the applied voltage exceeds the saturated value in each area. A large Q'_eff or lower N_a results in a large I_dsat in two areas due to the large absolute value of the threshold voltages V_thc and V_thu. The saturated current is approximately zero when only the uncovered channel works in this case, as shown by the green lines of Fig. 6(a). The deformation sensitivity S is defined as the slope of the channel current curves and can be used to evaluate the electrical performance of the device when the gate moves laterally. The sensitivity S improves with an increase in the channel length L_ch. For an air gap Z_air of 0.25 μm, S increases from 13.144 to 17.140 μA·μm^–1 when L_ch decreases from 10 to 2 μm. However, the device operation stability should be considered, because a small device size can result in a large potential field between the drain and source electrode and can easily break down the device. The air gap Z_air has a very large effect on the channel current I_ds and sensitivity S. For the device with a channel width W_ch of 10 μm and a channel length of 5 μm, the channel current I_ds increases from 1509.744 to 1796.400 μA when Z_air decreases from 0.5 to 0.1μm. However, S decreases from 34.634 to 8.314 μA·μm^–1 during this period, as shown in Fig. 6(b). This condition indicates that the output produced from undesirable vertical movement can be several times greater the current change from lateral movement. Therefore, a decoupling design is required to eliminate the interference from vertical movement, as discussed in the next section.

Fig. 6. Relationship between the saturated channel currents I_dsc and I_dsu, and the electrical parameters and geometry parameters at different width positions. (a) Net concentration of ionized acceptors in the substrate Na with effective channel charge density Q'_eff; (b) channel length L_ch and air gap Z_air. L_ch is 5 μm and Z_air is 0.25 μm for (a), and Q'_eff is 2.5 × 10^–8 C·cm^–2 and Na is 1 × 10¹⁵ cm^–3 for (b).

The proposed sensor utilizes an epoxy-type polymer photoresist, SU-8, as the structural material, which is an ideal material to fabricate LMGFET devices for the following reasons: First, SU-8 has a relatively low elastic modulus of 4–5 GPa, high mechanical strength, and stable chemical stability after ultraviolet (UV) exposure[33,34]. Second, SU-8 is a negative thick-film photoresist and can be used fabricate structures with a high aspect ratio [35]. These features make SU-8 suitable to serve as the structural material of laterally movable structures. Third, it is easy to uniformly deposit SU-8 on the substrate by utilizing a spin-coater or spray-coater, even for unleveled surfaces [36]. Finally, SU-8 can be easily patterned by UV exposure and developed in a propylene glycol methyl ether acetate solution, which is very much considerably more operable than etching materials, such as metal and silicon. In this research, an SU-8-based LMGFET force sensor with a movable sandwich structure is proposed, as discussed in the following section.

The movable structure and the substrate are two main components in the device, as shown in Fig. 7(a). The movable structure contains a probe and a center mass supported by straight beams. Fig. 7(b) shows the sandwich gate structure in which a gold gate electrode layer is fully covered by two photoresistive SU-8 layers. Gold is a common metal material in most labs and has been demonstrated to have excellent adhesion to SU-8 [37]. The thickness of the lower SU-8 structural layer should be small in order to decrease the effective gate gap and effective capacitance. Two series of gold gate arrays, S1 and S2, are set in the center mass with an offset distance D_off. In each series, two gate arrays lie symmetrically about with respect to the lateral lines Line_1 and Line_2. The gates in two series have the same width W_g and length L_g. The corresponding drain, source electrodes, and gate insulator layer are positioned underneath the gate arrays. The channel region has width W_ch and length L_ch and lies between the drain and the source electrode. In the initial state, the gate covers half of the channel width, as shown in Fig. 7(c).

Fig. 7. Schematics of the proposed LMGFET force sensor. (a) Movable structure design; (b) movable sandwich structure containing a gold gate array layer and two photoresistive SU-8 layers; (c) arrangement and dimension of the movable gate arrays. The coordinate axis direction in all 3D models is based on the principle that the positive direction of the Z-axis is from the upper movable structure to the substrate, the positive direction of the Y-axis is from the sensor probe to the end of the movable structure, and the positive direction of the X-axis is from the left side to the right side of the sensor. S1, S2: two series of gold gate arrays; Line_1, Line_2: lateral lines; W_g: gate width; L_g: gate length; D_off: offset distance.

When a lateral force F_Y is applied at the probe, the beams are involved in bending deformation. The gate arrays in the center mass move laterally and change the width of the channel area, which is expressed as follows: 

where is the structure deformation along Y-axis under F_Y ; E is the Young’s modulus of the structural materials;  is the moment inertia of the beam vertical section; and L_b, W_b, and T_b are the length width, and thickness of the supporting beam, respectively. When a vertical force F_Z is applied, the structure experiences a vertical force applied at mass center F'_Z and a force-induced moment  (where L_p is the probe length and L_m is the center mass length), which involve a vertical translation Z_F and a rotation around the X-axis for mass θ_X , as shown in Fig. 8; their expressions are 

where  is the moment inertia of the beam horizontal section. On this basis, a line with a distance of D_off exists away from the mass center line and has zero vertical displacement. This line is expressed as follows: 

Fig. 8. Translation and rotation movements of a movable structure under vertical forces. Z_F, θ_X : vertical translation and rotation around the X-axis for mass, respectively.

The vertical displacement of the gate series from force F_Z is expressed as follows:

where ±D is the offset distance of the center lines between the gate array and mass, the minus sign before the D refers to the upper gate arrays in S2, and the plus sign refers to the downside gate arrays in S2. The deformation ratio between the lateral and vertical forces can be written as follows:

A high r is achievable for structures whose thickness T_b is larger than the width W_b. Line_2 should be set at this D_off position, and the gate series S2 should be close to Line_2 in order to decrease undesired vertical movement. The straight beams cannot suppress or stretch. Thus, the structure rarely deforms along an X-axis force F_X. Therefore, the proposed movable structure will only be sensitive to force along the Y-axis and will be free from interference from other directions.

The proposed structure is simulated with ANSYS 15.0 to investigate its deformation behavior. The material and geometry parameters of the designed structure are given in Table 2. The geometry is modeled solely with an SU-8 structural layer, and the thin gold gate layer is ignored to reduce simulation complexity. In the simulations, the Young’s modulus and Poisson’s ratio of the SU-8 photoresist is 4.4 GPa [38] and 0.22 [39], respectively. The end of each beam is fixed, and a 1 nN force along the Y-/Z-axis is applied to the sidewall of the probe tip. Fig. 9 illustrates the deformation of gate series S2 under such forces. When a 1 nN lateral force is applied, the corresponding deformation is 1.961 nm, which is consistent with the theoretical value of 1.964 nm. Compared with the lateral movement under a Y-axis force, lateral movement caused by a Z-axis force is ignorable, as its value is approximately 0.00087 nm. The zero vertical deformation position D_off is approximately 673 μm away from the mass center. The vertical deformation of the gate series S1 is approximately 0.001 nm. The deformation ratio r is 1964, demonstrating the low cross-axis coupling effect in this structure.

Table 2 Material and geometry parameters of the designed structure.

Fig. 9. Deformation of the movable structure under a 1 nN force. (a) Deformation of the gate series S1 under a force along the Y-axis; (b) deformation of the gate series S1 under a force along the Z-axis.

Although the proposed structure rarely undergoes cross-axis deformation, undesired vertical deformation will inevitably bring interference to the channel current. Aside from the decoupling movable structure design, a sensing configuration is required to eliminate the cross-axis output coupling. A differential sensing configuration is normally adopted to compensate for loads from non-operation directions and for external disturbances, such as temperature and humidity. However, this method is unsuitable for LMGFET sensing because vertical movement of gate arrays different according to their position. In this research, a novel dualdifferential sensing configuration is proposed, in which the underlying channel region is not aligned with the gate arrays but is distributed anti-symmetrically about the center of Line_1 and Line_2, as shown in Fig. 10. Each transistor series is separated into four arrays: S1_LU, S1_LD, S1_RU, and S1_RD are for series S1, while S2_LU, S2_LD, S2_RU, and S2_RD are for series S2. The interconnection configurations of S1 and S2 are illustrated in Figs. 11(a) and (b), respectively. S2 is for lateral force detection, and S1 is for vertical force detection. This paper focuses on lateral force detection. Thus, the following description is conducted with series S2. I_dsL is the sum of the current of two left transistor series S2_LU and S2_LD, and I_dsR is the sum of the current of two right transistor series S2_RU, S2_RD. These expressions can be written as follows:

where I_ds1, I_ds2, I_ds3, and I_ds4 are the current of the transistor series S2_LU, S2_LD, S2_RU, S2_RD, respectively.

Fig. 10. The proposed dual-differential sensing configuration. S1_LU, S1_LD, S1_RU, and S1_RD are transistor series for S1; S2_LU, S2_LD, S2_RU, and S2_RD are transistor series for S2.

Fig. 11. Schematic of the proposed dual-differential configuration. (a) Interconnection of gate series S1; (b) interconnection of gate series S2. D: the common drain electrode; S: the common source electrode; V_DD: voltage applied at the common drain electrodes; V_ss: voltage applied at the common source electrode; V_g: voltage applied at the common gate electrodes. R: resistor; I_dsU: the sum of the current of two left transistor series S2_LU and S2_RU; I_dsD: the sum of the current of two left transistor series S2_LD and S2_RD; I_dsL: the sum of the current of two left transistor series S2_LU and S2_LD; I_dsR: the sum of the current of two right transistor series S2_RU, S2_RD; I_ds1–I_ds4: the current of the transistor series S2_LU, S2_LD, S2_RU, S2_RD, respectively.

Most vertical interferences are counteracted in Eqs. (20) and (21). The final sensor output can be measured with the potential difference between two circuit branches, V_out = R × (I_dsL – I_dsR) (where R is the connected resistor in the readout circuit). The sensing performance of the proposed dual-differential configuration is illustrated in Fig. 12 and is compared with the normal differential method, where the channel region is aligned with the gate array. The difference between the initial output and that under the vertical displacement is measured with relative errors for the two methods, as shown in Figs. 12(a) and (b). 

Fig. 12. Sensing performance of the proposed dual-differential configuration under different saturated voltages. (a) Channel current at saturated drain voltage V_dsc; (b) channel current at saturated drain voltage V_dsu. Straight lines indicate the output current under 0 nm vertical displacement, scatters indicate the output under different vertical displacements, and dashed lines with scatters represent the relative output error of the two sensing configurations.

For a 1 nN force loaded in the sensor probe, the sandwich structure moves 1.961 nm laterally but 0.001 nm vertically. Therefore, the vertical displacement is set from 0.001 to 3.000 nm in order to investigate the sensing performance under vertical forces ranging from 1 nN to 3 μN. The relative errors of the two methods are negligible for a small vertical displacement of less than 0.03 nm. Because of the rapid increased C'_effu, the relative error of the differential channel current increases until W_chc reaches 7.5 μm. The relative error of the normal differential method at V_dsc reaches 4.53% for a 3 nm vertical displacement, and that of the proposed method is less than 0.01%. When W_chc reaches 10 μm, the relative errors solely resulting from the covered area exhibit a drop because C'_effu disappears. V_dsu has a higher change rate than V_dsc because C'_effu is more susceptible to air gap size than C'_effc; the relative errors at V_dsu show an increase compared with those at V_dsc, as shown in Fig. 12(b). The relative errors of the normal differential method at V_dsu increase to 2.24% and 4.76% for vertical displacements of 0.03 and 3.00 nm, respectively, but the largest relative error of the proposed configuration remains as low as 0.43%. Considering the deformation behavior of the movable structure, a 3 nm vertical deformation of the gate series S1 demands a vertical force of 3 lN. The gate series cannot deform at 3 nm because the mass end face could touch the substrate under vertical forces below such a value. Therefore, the cross-axis coupling effect is thoroughly eliminated in the proposed dual-differential sensing configuration.

A simple but practicable fabrication is proposed for the presented LMGFET device, as shown in Fig. 13. A photoresist layer is deposited and patterned to define the drain and source electrode and its interconnections; the substrate is then ion-implanted to form phosphorus-doped areas. Through another patterned photoresistive layer, the channel area is defined and then doped with phosphorus ions but using different implantation doses and energies. The implanted ions are activated through rapid thermal annealing. A gate insulation layer made of silicon nitride is deposited and then patterned to expose contact holes for source/drain interconnections. Subsequently, a sacrificial layer of silicon dioxide is deposited and patterned to expose the structure anchors and contact holes. A thin SU-8 structural layer is spun, exposed, and developed to act as the lower layer of the sandwich structure. A gold layer is then deposited and patterned to act as the gate arrays and pads of the drain and source electrodes. The substrate metal pad is formed through another gold layer deposited on the bottom side of the chip. Another thick SU-8 layer is spun to seal the gate array and is patterned for the upper sandwich structural layer. The substrate is patterned with deep reactive ion etching to expose the probe area. Finally, isotropic etching of the sacrificial silicon dioxide layer is conducted to release the movable sandwich structure.

Fig. 13. Flow chart of the proposed fabrication process.

The fabrication process is simulated using FEM Software Sentaurus 13.0; the adopted parameters are illustrated in Table 3 and the simulated LMGFET unit is shown in Fig. 14(a). The device is modeled as a single transistor to simplify the computation complexity, and the air gap and lower SU-8 structural layer are replaced with an effective silicon dioxide layer by using the following expression: 

where T_{low_SU-8} and ε_SU-8 are the thickness and permittivity of the lower SU-8 layer, and is the permittivity of silicon dioxide. The peak implanted ion concentration in the channel area is 1 × 10¹⁷ cm^–2 , which is achievable in the bath fabrication process as discussed in our previous work [25]. The characteristic of how the distribution of channel impurities influences the channel current is investigated by setting different ion implantation depths from 0.150 to 0.300 μm. Fig. 14(b) shows a cross-section view of the activated implanted phosphorous distribution at an implantation depth of 0.275 μm. The inset shows the extracted concentration profile of active phosphorus in the channel region for the device in Fig. 14(a). A rectangular approximation is modeled to describe the concentration profile, as shown by the read dotted line in Fig. 14(b). The effective channel charge density Q'_eff is set as the product of the peak phosphorus density and the effective implantation depth. Table 4 lists the derived electrical parameters at different implantation depths. 

Table 3 Parameters in fabrication simulation.

Fig. 14. Simulation of the proposed fabrication process. (a) 3D LMGFET unit in the simulation. (b) Implantation concentration in the simulated device; (upleft) extracted implantation ion profile along the dotted line in the channel area. X'_eff: the effective implantation depth. 

Table 4 Extracted parameters under different implantation depths.

Four different electrodes are set in the gate, source, drain, and substrate region and modeled as red grids to investigate the electrical output behaviors, as shown in Fig. 14(a). A voltage of 0 is applied to the gate, source, and substrate electrodes, because the fabricated transistor is a depletion-type device. Fig. 15(a) shows the channel output current I_ds characteristics under different channel implantation profiles when the applied drain voltage V_ds increases from 0 to 20.5 V. When the implantation depth is 0.15 μm, the theoretical dotted line agrees well with the solid simulated line throughout the whole voltage range. The difference between the theoretical and simulated lines increases as the implantation depth increases. More specifically, the calculated current is smaller than that of the simulation for a low drain voltage, indicating that the proposed model is conservative in the nonsaturation region. This characteristic is associated with the errors from the implantation approximation. However, the saturation region exhibiting the maximum controllable measuring sensitivity is the focus of this research, in which the theoretical calculation and simulations are in excellent accordance for all implantation depths. The calculated channel current is compared with the simulated one at the saturated voltages V_dsc and V_dsu; their relative errors are all less than 2% and are shown in Fig. 15(b).

Fig. 15. Channel output current I_ds characteristics under different implantation depths. (a) Relationship between channel current I_ds and applied drain voltage V_ds; (b) saturated channel current I_ds and the corresponding relative errors between the calculated and simulated results. Solid lines indicate the simulated channel current, while dotted lines indicate the calculated channel current.

The theoretical model is validated using the experimental data from Ref. [24] and is compared with the literature-adopted model, which assumes a constant effective gate capacitance in the uncovered channel area C'_effu and utilizes a regulation parameter for estimating the modulation effects. The experimental parameters extracted from Ref. [24] are listed in Table 5. In this study, the effective gate capacitance in the uncovered channel area C'_effu is constant and derived from the covered width W_chc of 18 μm. In fact, C'_effu should increase with the increase in W_chc, as discussed in Section 2. Fig. 16 provides a comparison of the calculated channel current from the proposed model and the model in Ref. [24]. The two models show similar accuracy for 18 μm W_chc. The proposed model presents a close estimation for the outputs under the covered channel widths W_chc of 0 and 60 μm. The largest relative error of the proposed model is 1.51% for a W_chc of 0 and 2.63% for a W_chc of 60 μm. However, those of the improved model are 6.64% and 5.84%, respectively. Therefore, the proposed model is more accurate than the previous model for LMGFET performance analysis. 

Table 5 Experimental parameters of the fabricated LMGFET device [24].

Fig. 16. Theoretical calculation and experimental measurement of channel current Ids. (a) Gate fully uncovers the channel area, W_chc = 0 μm; (b) gate partially covers the channel area, W_chc = 18 μm; (c) gate fully covers the channel area, W_chc = 60 μm.

For sensor performance evaluation, the output channel current of the proposed sensor is obtained at different gate positions. Fig. 17 presents the saturated channel currents I_dsatc and I_dsatu of the simulations and calculation for an implantation depth of 0.275 μm. The saturated voltages V_dsatc and V_dsatu are set to 10.2 and 12.1 V, respectively, which are the lowest values during sensor operation. The relative error between the theoretical and simulated saturated currents is 3.88% and 5.64% at 0 μm W_chc. The mismatch under the condition of a small covered channel width mainly results from the estimation error of the capacitance expression (Eq. (2)). The relative error becomes less than 3.80% for W_chc > 1 μm. The sensitivity of the proposed device is 8.39 and 9.12 μA·nN^–1 for the saturated voltages V_dsatc and V_dsatu, respectively. Due to the low stiffness of the SU-8 movable structure, the force sensitivity of the proposed LMGFET sensor is 4.65 μA·nN^–11 , which is lower than that of our previous VMGFET device, which had a value of 12.53 μA·nN^–1 [25]. Nevertheless, it is much higher than those of previous VMGFET devices with values of 3.24 [22] and 0.05 μA·nN^–1 [23], and higher than that of a reported LMGFET device with a value of 0.01 μA·nN^–1 [24]. The nonlinearity experiences a slight fluctuation because the transistor in either the covered channel area or the uncovered area disappears when the channel is fully covered or exposed. The nonlinearity approaches 0.19% and 0.78% for a W_chc ranging from 2.5 to 17.5 μm and from 1 to 19 μm, respectively, which is much less than that of existing MGFET devices. The measurement range of the proposed sensor is ±5.10 μN, which is relatively less than that of the LMGFET device in Ref. [24] but much larger than those of VMGFET devices[22,23,25]. 

Fig. 17. Theoretical calculation and experimental measurement of channel current I_ds under different channel widths W_chc.

To evaluate the overall sensing performance, the product of the sensitivity, linearity, and measurement range is calculated as a merit factor, as shown in Table 6[22–25]. The proposed sensor exhibits the largest merit factor of 47.07 mA among existing MGFET devices, indicating that a delicate tradeoff has been made between high sensing accuracy and a large measurement range for the proposed sensor. All these characteristics make the proposed sensor a suitable choice for the measurement of ultralow forces below the nano-newton level, especially for biomedical applications requiring a large measurement range, such as cell deformation squeezing and cellular membrane penetration.

Table 6 Performance comparison with existing MGFET devices.

Na: not available.

^a Sensitivity is unified into the same unit.

In this paper, an LMGFET micro force sensor was proposed and comprehensively analyzed. The electrical behavior of the small LMGFET unit was theoretically modeled into two individual parts and tested with simulations and experimental data. The proposed sensor exhibited improved accuracy and capability for device performance evaluation before mass fabrication. A novel sandwich structure containing a gold gate array layer and two covered SU8 photoresist layers was developed by decoupling multiple gate arrays and using a dual-differential sensing configuration. The output current under cross-axis loadings was considerably suppressed. The electrical and structural parameters of LMGFET devices were fully analyzed in order to optimize the sensor performance, and a practicable fabrication process was developed and simulated. The proposed sensor exhibits considerably high sensitivity, linearity, and a large measurement range, making it a versatile sensing tool for biomedical micromanipulation tasks. 

This work is supported in part by the National Natural Science Foundation of China (52105589 and U1909221), in part by the China Postdoctoral Science Foundation (2021M692590), in part by the Beijing Advanced Innovation Center for Intelligent Robots and Systems (2019IRS08), in part by the Fundamental Research Funds for the Central Universities (China) (xzy012021009), and in part by the State Key Laboratory of Robotics and Systems (HIT) (SKLRS2021KF17).

Wendi Gao, Zhixia Qiao, Xiangguang Han, Xiaozhang Wang, Adnan Shakoor, Cunlang Liu, Dejiang Lu, Ping Yang, Libo Zhao, Yonglu Wang, Jiuhong Wang, Zhuangde Jiang, and Dong Sun declare that they have no conflict of interest or financial conflicts to disclose.