This article proposes and demonstrates a retrodirective array (RDA) for two-way wireless communication with automatic beam tracking. The proposed RDA is enabled by specifically designed chips made using a domestic complementary metal-oxide semiconductor (CMOS) process. The highly integrated CMOS chip includes a receiving (Rx) chain, a transmitting (Tx) chain, and a unique tracking phase-locked loop (PLL) for the crucial conjugated phase recovery in the RDA. This article also proposes a method to reduce the beam pointing error (BPE) in a conventional RDA. To validate the above ideas simply yet without loss of generality, a 2.4 GHz RDA is demonstrated through two-way communication links between the Rx and Tx chains, and an on-chip quadrature coupler is designed to achieve a non-retrodirective signal suppression of 23 dBc. The experimental results demonstrate that the proposed RDA, which incorporates domestically manufactured low-cost 0.18 μm CMOS chips, is capable of automatically tracking beams covering ±40° with a reduced BPE. Each CMOS chip in the RDA has a compact size of 4.62 mm2 and a low power consumption of 0.15 W. To the best of the authors’ knowledge, this is the first research to demonstrate an RDA with a fully customized CMOS chip for wireless communication with automatic beam tracking.
Beam directive communication has emerged as a topic of significant global interest and research, owing to its remarkable potential for enhancing signal strength and spatial efficiency. By leveraging advanced antenna array technologies, electromagnetic waves can be focused in specific directions for transmission and reception, thereby maximizing the signal power in the intended direction while suppressing interference from other directions. This capability holds tremendous promise for various applications, including wireless communication and radar, in which improved signal quality, increased coverage, and enhanced spectral efficiency are desired [1], [2], [3]. Conventional phased-array architectures employ phase-shifting techniques to achieve beam steering for many application scenarios [4], [5], [6], [7], [8]. However, the utilization of phase shifting in both the radio frequency (RF) and digital baseband stages introduces inherent control complexities and associated costs.
To alleviate this challenging issue, retrodirective arrays (RDAs) possess the distinct capability of autonomously tracking incoming signals and retransmitting them backward to the source [9], [10], [11]. Unlike phased arrays, RDAs perform real-time tracking and beam steering without requiring prior knowledge of the source position. Moreover, RDAs avoid the need for complex digital signal-processing (DSP) algorithms, which often impose significant demands in terms of computation time and power resources [12]. By leveraging the inherent advantages of RDAs, such as their simplified architecture and real-time tracking, researchers and engineers seek to overcome the limitations of conventional phased arrays and advance the field of beam directive communication systems. RDAs are promising for mobile communication systems, especially in the context of aircraft and satellites [13], [14], [15], [16], [17], due to their capability to establish an automatically adaptive communication link with moving platforms. RDAs have also attracted the attention of researchers in the fields of radio-frequency identification (RFID), sensors, and radar applications, among others [18], [19], [20]. Moreover, communication systems employing RDA technology provide additional data protection against interception from undesired directions, even in environments with multiple signal paths [21], [22].
RDAs are mainly categorized into two types, based on their implementation principles: non-phase-conjugating RDAs and phase-conjugating RDAs. The non-phase-conjugating structure, commonly known as the Van Atta type [23], achieves signal retrodirectivity by symmetrically positioning delay lines between antenna pairs, as depicted in Fig. 1(a). In contrast, the Pon type [24] employs mixers to achieve phase conjugation [25], as depicted in Fig. 1(b). Through this method, the retransmitted signals undergo coherent addition in the direction of the incoming waves. Notably, Pon-type structures exhibit flexibility in terms of element placement compared with their Van Atta counterparts. However, conventional Van Atta and Pon RDAs do not support two-way communication, as they are limited to receiving continuous wave (CW) signals rather than modulated signals [26], [27]; they also suffer from unavoidable beam pointing errors (BPEs). Moreover, the RDAs reported in the literature rely on bulky, discrete modules, resulting in a large and cumbersome system size [28], [29], [30], [31], [32], [33].
To address the above issues, this article proposes a highly integrated RDA for two-way communication. The proposed RDA is capable of achieving automatic beam tracking and steering, thus establishing a stable two-way communication link, as shown in Fig. 1(c). The tracking phase-locked loop (PLL) in the highly integrated complementary metal-oxide semiconductor (CMOS) chip demonstrates the capacity to recover the essential conjugated phase of the RDA after the modulated information is removed. The main contributions of this article are: ① the first presentation of an RDA enabled by specifically designed CMOS chips for wireless communication; ② the first implementation of lumped-element quadrature couplers on a chip to suppress unwanted non-retrodirective signals in an RDA; and ③ the first presentation of a method to reduce the BPE of an RDA retransmitted beam.
The remainder of this article is organized as follows. Section 2 provides an analysis of the proposed RDA and presents its system architecture. Section 3 analyzes and presents a method to reduce the BPE of the RDA. Section 4 describes the building-block circuit design of the specifically designed CMOS chip. Section 5 provides the experimental results for the CMOS chip and the proposed RDA. Finally, Section 6 concludes this article.
2. The proposed RDA architecture
As shown in Fig. 2, the proposed RDA comprises specially designed low-cost CMOS chips, a left-handed circularly polarized (LHCP) antenna array for receiving signals from a mobile user, and a right-handed circularly polarized (RHCP) antenna array for retransmitting signals. Each antenna element is connected to a CMOS chip and then linked to the corresponding element in the transmitting (Tx) array. The channels in the proposed RDA are identical, facilitating the easy expansion of the proposed RDA into a large-scale one-dimensional (1D) or two-dimensional (2D) array.
The signal-processing tasks, including phase conjugation, are implemented using CMOS chips. The phase conjugation required by the Pon-type RDA is realized by a down-converting mixer behind the low-noise amplifier (LNA). The input signal cosωRFt, with phase ϕ is applied to the mixer, is mixed with a local oscillator (LO) signal (cosωLO1t). The output of the mixer is as follows:
where vIF is the intermediate-frequency (IF) signal, VRF is the amplitude of the input signal, ωRF is the frequency of the input signal, ϕ is the phase of the input signal, VLO1 is the amplitude of local oscillator signal, and ωLO1 is the frequency of local oscillator signal.
After passing through a low-pass filter, the high-frequency component is filtered out, and the second term of Eq. (1) with the conjugate phase (−ϕ) is retained.
The utilization of a Pon-type structure in two-way communications presents the challenge of accurately recovering the conjugate phase (−ϕ) of the carrier while simultaneously removing the modulated data. To address this challenge in a straightforward manner, the proposed RDA adopts amplitude-modulated (AM) signals as the receiving (Rx) signals. This choice is motivated by the fact that data modulation primarily affects the signal’s amplitude rather than its phase. Within the CMOS chip, a shaping circuit is employed to convert the amplified IF1 signal into a square wave signal, thereby removing the AM data (as detailed in Section 4).
A phase-frequency detector (PFD), charge pump (CP), loop filter (LF), and quadrature voltage-controlled oscillator (QVCO) form a tracking PLL, which is capable of recovering the phase of the IF1 square wave signal. The QVCO can reproduce a high-power, low-phase noise signal for retransmission. This signal is in the same frequency and phase as the IF1 signal:
where vVCO is the output signal of the QVCO, VVCO is the amplitude of the QVCO signal, and ωVCO is the frequency of the QVCO signal.
Unlike normal voltage-controlled oscillators (VCOs), QVCOs are capable of generating quadrature signals directly, without the need for quadrature couplers. The QVCO provides quadrature signals for the two up-converting mixers, respectively. The output of mixer A is as follows:
where vA is the output signal of mixer A, vB is the output signal of mixer B, VIF2 is the amplitude of the IF2 signal, and ωIF2 is the frequency of the IF2 signal.
The upper sideband of the mixer output with the conjugate phase −ϕ is the required part of the RDA, while the lower sideband of the mixer output with the phase +ϕ is the non-retrodirective part. Separating the two parts on-chip is challenging, due to the difficulty of implementing an on-chip band-pass filter with a high Q factor. The proposed specifically designed CMOS chip adopts an on-chip quadrature coupler to suppress the non-retrodirective part. After passing through a coupler, the output of mixer B becomes
The second terms of Eqs. (3), (5) lie at 180° with respect to each other; therefore, they cancel each other out, since they are in antiphase. The output of the coupler is VVCOVIF2cos((ωIF2+ωVCO)t-ϕ), which only contains the upper sideband with the conjugate phase −ϕ. Following that, the signal is amplified by a power amplifier (PA) and transmitted by an RHCP antenna. Since the phase −ϕ is conjugated with the phase of the input signal, the Tx array steers the beam in the direction from which the pilot signal is incoming.
3. Analysis of the BPE
In practical applications of RDAs, it has been observed that the angle of the retransmitted beam deviates from the angle of the received pilot beam. This deviation, commonly referred to as the BPE, tends to increase as the angle of the received pilot signal arriving at the array becomes larger. The BPE is an important parameter for an RDA. In typical scenarios, the maximum acceptable BPE for an RDA is 5° [34]. However, in specific applications, the requirements for the BPE may vary. For example, satellite communications necessitate a BPE that is less than 5% of the beamwidth.
For the conventional RDA shown in Fig. 3(a), the active element approach (Eq. (6)) proposed in Ref. [35] can be used to accurately obtain the pattern ERDA:
As shown in Fig. 3(a), N is the total number of antenna elements; j is the imaginary part; λ is the wavelength of signal; ϕr is the angle of the received pilot signal arriving at the array with a given bistatic scan angle; xi is the distance of the ith element from the center of the array; ϕt is the azimuth angle, used as an independent variable in the calculation of ERDA; ψ is the constant path length; and gci(ϕt) and Ii are the ith individual active element pattern and feed current, respectively.
As shown in Fig. 3(b), two different antenna arrays are designed for different receiving and retransmitting frequencies; therefore, Eq. (6) must be modified as follows:
As shown in Fig. 3(b), λt and λr are the wavelengths of the retransmitted and received signals, respectively; xti and xri are the distances of the ith element from the center of the Tx array and the Rx array, respectively; and gcit(ϕt) represents the ith individual active Tx element pattern.
When λt, λr, xti, and xri satisfy Eq. (8), the pointing error caused by the unequal wavelengths is removed. However, actual antennas (e.g., patch antennas)—instead of ideal isotropic antennas—also introduce a BPE. gcit(ϕt) of the antenna element introduces a decrease in gain at angles off the boresight, which causes the retransmitted beam to point at an angle less than ϕr [34]. Moreover, as the angle of arrival, ϕr, increases, the BPE introduced by gcit(ϕt) also increases. Increasing the array size or the beamwidth of the antenna elements can reduce the BPE caused by gcit(ϕt). However, expanding the array size increases the costs, and increasing the beamwidth of the antenna elements is constrained by physical conditions.
The proposed RDA reduces the above BPE by optimizing dt of the Tx array. When the number of array elements N is even, the spacing dt is 2xti/(2i − 1). When the number of array elements N is odd, dt is xti/i. According to Eq. (7), in order for ERDA to reach the maximum, sinϕt increases as xti decreases, which means that the pointing angle of the retransmitted beam increases as dt decreases. Therefore, the BPE caused by gcit(ϕt) is cancelled out.
In this work, circularly polarized patch antenna arrays are implemented to validate the analysis of the BPE and the proposed RDA. For simplicity yet without loss of generality, the LHCP Rx and RHCP Tx antenna arrays are designed to operate at 2.4 and 2.5 GHz, respectively. Their orthogonal polarization improves the isolation between the receiving and transmitting front-ends. For the purpose of easy BPE comparison, each array was designed in a 1D configuration, comprising 4 × 1 truncated radiated microstrip patches, implemented in Rogers RO4003C with a relative permittivity of 3.55.
The array element spacing (dr) of the Rx array is set to 75 mm. The simulated retransmitted signal angles of the Tx array with different spacing (dt) versus the received signal angles can be obtained using the electronic design automation (EDA) software, as shown in Fig. 4(a). This analysis also incorporates the consideration of mutual coupling among the Tx antenna elements. The array element spacing of 72 mm is calculated from Eq. (8). When the spacing of the Tx array is set to 68 mm, the simulated BPE becomes smaller compared with that of the Tx array with a spacing of 72 mm. Further reducing dt increases the beam pointing angle of the retransmitted signal; this causes it to exceed the receiving signal angle, thereby increasing the BPE, as shown in Fig. 4(b). Consequently, a spacing of 68 mm is chosen for the 2.5 GHz Tx array.
4. Key building blocks
To validate the proposed architecture, a highly integrated circuit chip was implemented using domestic low-cost 0.18 μm CMOS technology. The CMOS chip was operated within 2.4 GHz for the demonstration. Fig. 5(a) illustrates the design of the differential common-gate (CG) amplifier serving as the LNA. As shown in Fig. 5(b), the proposed CG LNA features broad input matching. The LNA employs a capacitor cross-coupled CG structure, which—as a gm-boosting technique—contributes to an enhanced gain and a reduced noise figure (NF) [36]. Differential signals of opposite polarity are coupled to the gates of the transistors through capacitor Cc, which increases the gate-to-source voltage swing and increases the effective transconductance Gm of the transistors. The Gm of the transistors in the capacitor cross-coupled CG structure is as follows:(9)Gm=1+Agm=Cgs+2CcCgs+Ccgm
That is, Gm is (1 + A) times the original gm, and A is equal to Cc/(Cc + Cgs), where Cgs is the parasitic capacitance from gate to source. When Cc ≫ Cgs, A is maximized to 1; that is, Gm is up to twice the original gm. The noise factor decreases as the effective transconductance and gain increase. The noise factor F1 of the structure is 1 + (F − 1)/(1 + A), where F is the noise factor of a conventional CG amplifier. The simulated minimum NF (NFmin) is presented in Fig. 5(c). It can be observed that NFmin decreases as Cc increases. However, as Cc exceeds 2 pF and continues to increase, the reduction in NFmin becomes less significant. In order to achieve improved noise performance without significantly increasing the layout area, Cc is chosen to be 2 pF. Symmetrical inductors, L1 and Lin, are selected with the respective values of 19.00 and 4.48 nH.
A schematic of the proposed down-converting mixer with an active balun is shown in Fig. 6(a). The p-channel transistors M3 and M4 are used as a bleeding current source, as well as a part of the transconductance amplifier stage. The Gm of the transconductance stage (gmn + gmp; where gmn is the gm of n-metal-oxide-semiconductor transistor and gmp is the gm of p-channel metal-oxide-semiconductor (PMOS) transistor) is increased by the PMOS, reducing the noise and increasing the gain [37]. The LO signal controls the gates of M5-M8 for switching. An additional bleeding current source also allows the required current through the switching stage to be reduced, so that the load resistance can be larger to increase the gain. Resistor-capacitor (RC) parallel-connected structures are used as loads of the mixer and the output buffer. Capacitors connected to VDD suppress RF and LO leakage and high-frequency mixing products, while preserving the low-frequency mixing products with a conjugating phase. An active balun composed of a CG/common-source amplifier pair is designed to supply the differential LO signal to the mixer. The common-source amplifier generates an inverted output signal at the drain compared with the input signal, while the CG amplifier produces an in-phase output signal with the input signal, resulting in a 180° phase difference. The imbalance of the balun is further minimized through capacitor and biasing optimization. Compared with passive baluns, active baluns offer a wider operating bandwidth and a more compact chip area. The simulation results of the balun are shown in Fig. 6(b).
As shown in Fig. 7(a), a Schmitt trigger is designed as the shaping circuit, following a common-source amplifier stage. The use of four series-connected inverters ensures the conversion of the input waveform into a square wave, effectively eliminating amplitude modulation. Subsequently, this square wave is utilized as the reference clock signal for the PFD. R2 acts as a feedback resistor. Fig. 7(b) shows the waveform conversion process of the shaping circuit. The threshold voltages VT+ and VT− are (1 + R1/R2)Vth and (1 − R1/R2)Vth, respectively, where Vth is the threshold voltage of the inverter; With this feature, the Schmitt trigger can output an ideal square wave signal and effectively resist the interference caused by input voltage fluctuations. R1 and R2 are chosen to be 300 Ω and 10 kΩ, so that VT+ and VT− are respectively 0.93 and 0.87 V.
The edge-triggered PFD uses modified D-flip-flops (DFFs) and an AND gate, as shown in Fig. 8(a). The time delay of the AND gate determines the width of the reset pulses. Through appropriate design, the DFF-type PFD can eliminate the dead zone and achieve a phase detection range of ±360°. A CP with dynamic negative feedback can decrease the charge and discharge current mismatch, as shown in Fig. 8(b). For example, when the output voltage Vtune increases, by a cross connect of M9-M10 and M14-M15, the gate voltages of M18-M19 are simultaneously suppressed to adjust the charge and discharge current match. Without an operational amplifier (OP-AMP), this CP is more energy efficient.
A ring oscillator is designed to provide quadrature signals to mixers A and B while providing a feedback signal to the PFD. It is composed of four differential dual-delay cells with a 90° delay, as shown in Fig. 9(a). The differential structure has the advantage of reducing the power-supply-injected phase noise [38]. A dual-delay structure is implemented to achieve a wider tuning range, as shown in Fig. 9(b). The negative skewed delay paths are represented as blue lines in the figure, while the normal delay paths are shown as black lines. The negative skewed delay paths are connected to the two stages before the current delay stage. Simple inverters are used to isolate the output ports and the delay cells. The simulated tuning range of the QVCO is 25-144 MHz.
Fig. 10 illustrates the schematic of the mixers, A or B. Their structure is basically the same as that of the down-converting mixer given in Fig. 6(a). An LC parallel-connected structure is used as the load of the mixer and is tuned at 2.5 GHz. The differential input signals of both mixer A and mixer B are provided by the same active balun, whose design is identical to the active balun shown in Fig. 6(a). The differential LO signals are provided by the QVCO, as shown in Fig. 9(b).
The structure of the proposed lumped-element quadrature coupler is shown in Fig. 11(a). Ports 2, 3, and 4 are the direct port, coupled port, and isolated port, respectively. The parasitic capacitance of the wires (Cp) is also taken into consideration. L1 and C1 are chosen to be 3.3 nH and 866 fF. Compared with a coupler consisting of quarter-wavelength transmission lines, the proposed coupler occupies a very small chip area of 0.22 mm2. Therefore, lumped-element quadrature couplers are well suited for the on-chip integration. Figs. 11(b) and (c) shows the simulated S-parameters of the proposed lumped-element quadrature coupler. The simulated |S21| and |S31| are −4.1 dB at 2.5 GHz. The loss of couplers can be reduced by implementing higher Q passive devices.
Fig. 12(a) illustrates the class-A PA, which employs the cascode configuration to further amplify the out signal. A capacitor-inductor-capacitor network is employed at the input port to match to the quadrature coupler. The simulated gain and the output 1 dB compression point of the PA are respectively 19 dB and 7.9 dBm at 2.5 GHz, as shown in Figs. 12(b) and (c).
5. Implementation and experiments
Various measurements were meticulously conducted to comprehensively assess the performance of the proposed RDA, including CMOS chip measurement, a two-way communication performance evaluation of the chip, and a beam steering measurement specifically aimed at gauging the retrodirective performance of the RDA. Lastly, a real-time wireless communication demonstration featuring video transmission was conducted, highlighting the capability of the system for mobile communication.
5.1. Measurement of the CMOS chip
The specially designed circuit chips were fabricated using a low-cost 0.18 μm CMOS process; each chip has the dimensions of 1.4 mm × 3.3 mm, including all pads. Fig. 13 provides the die microphotograph of a fabricated CMOS chip. There are many filling blocks in the chip to comply with the design rule check (DRC). The fabricated CMOS chip was further mounted on an FR-4 printed circuit board (PCB) with a thickness of 0.5 mm.
The total power consumption of the chip was measured to be 151.2 mW with a voltage supply of 1.8 V. The performance of the LNA and down-converting mixer was evaluated first. Fig. 14(a) displays the measured output power of the mixer versus the input power of the LNA, with an input frequency of 2.4 GHz and LO1 frequency of 2.45 GHz. The LO1 signal power level at the active balun input port was set as 0 dBm. The receiving front-end demonstrated a conversion gain of 21.3 dB around 2.4 GHz, with an input 1 dB compression point of −29 dBm. Fig. 14(b) illustrates the simulated and measured QVCO output frequency versus the control voltage. The QVCO can be tuned from 25 to 135 MHz when its control voltage changes from 1.2 to 1.8 V. As shown in Fig. 15(a), the measured phase noise of the QVCO was −93 dBc·Hz−1 at 100 kHz. This low phase noise does not seriously affect the BPE.
Fig. 15(b) presents the measured spectrum of the PA output signal. The QVCO frequency was set to 50 MHz, and the IF2 frequency was set to 2.45 GHz. In the spectrum, the upper sideband (USB) corresponds to the desired signal, while the lower sideband (LSB) represents the non-retrodirective signal. After calibration, the measured output power of the desired signal was 0 dBm, and the measured LSB suppression was 23 dBc.
The sensitivity of the CMOS chip was evaluated using the setup shown in Fig. 16(a). The LO1 signal and the IF2 signal were both set to 2.45 GHz. The tracking PLL of the chip operated properly when the input signal frequency ranged from 2.37 to 2.42 GHz, resulting in an output signal frequency range of 2.47-2.52 GHz. The measured sensitivity of the CMOS chip was around −54 dBm. When the input power was below this sensitivity level, the tracking PLL failed to recover the phase of the IF1 carrier. The sensitivity value is primarily limited by the conversion gain of the IF amplifier. To achieve better sensitivity, a multi-stage amplification configuration or a high-gain amplification structure can be implemented for the IF amplifier.
To evaluate the communication capability of the proposed CMOS chip, a two-way communication measurement was conducted, as depicted in Fig. 16(b). A universal software radio peripheral (USRP) connected to a computer was used to modulate/demodulate signals. In this measurement setup, the input signal was amplitude modulated onto a carrier frequency of 2.4 GHz using a modulation index of 0.5. The USRP received the 50 MHz signal from the down-converting mixer for AM demodulation. As shown in Figs. 17(a), the AM demodulated waveform followed the 100 Kb·s−1 pseudorandom reference signal (Fig. 17(b)) quite well.
To assess the communication performance of the transmitter front-end, the IF2 signal was modulated with QPSK/16QAM onto a carrier frequency of 2.45 GHz. The 50 MHz carrier recovery signal from the QVCO was mixed with the modulated signal. The USRP received the 2.5 GHz signal from the PA for demodulation. The measured constellation diagram is presented in Fig. 18, indicating the performance of the demodulated signals.
5.2. Retrodirective performance
A beam-steering bistatic measurement was conducted to verify the automatic beam tracking capability of the proposed RDA, as depicted in Fig. 19. A 2.4 GHz LHCP microstrip patch antenna connected to a signal generator was utilized to transmit the pilot signal to the RDA. On the other side, a 2.5 GHz RHCP patch antenna connected to a spectrum analyzer was employed to receive the signal back from the RDA. The use of different operating frequencies and polarization states avoided direct power coupling from the Tx patch to the Rx patch. To precisely control the received signal angle of the RDA, the RDA’s Rx array was set at a fixed angle relative to the Tx patch antenna. The RDA’s Tx array under testing was then rotated in the azimuth plane to measure the radiation patterns.
Fig. 20 compares the simulated and measured radiation patterns corresponding to different received signal angles. The measured results indicate that the proposed RDA can automatically steer the beam pointing according to the direction of the pilot signal within a range of ±40°. Fig. 21 shows that the BPE of an RDA with a Tx array element spacing of 68 mm is smaller than that of an RDA with a spacing of 72 mm. These measurements confirm the effectiveness of the proposed method in reducing the BPE of the RDA, which can be applied to a wider range of RDA applications.
5.3. RDA wireless communication demonstration
As shown in Fig. 22, a wireless demonstration was performed in an indoor scenario to test the RDA’s performance in dynamic operation. In this setup, the Rx and Tx antennas were placed on a cart to simulate mobile user equipment (UE), while the RDA Tx and Rx arrays were positioned vertically on a turntable. The array element spacing of the Tx array was 68 mm. For the modulation and demodulation of signals, an NI USRP device was employed, and a signal generator was used to provide LO signals to the RDA.
The RDA Tx and Rx arrays were simultaneously rotated in the azimuth plane to measure the received power of the Rx antenna. The measured results presented in Fig. 23(a) demonstrate that the proposed RDA exhibits a 3 dB beamwidth of 90°. This wide beamwidth ensures that the mobile user consistently receives a high level of power over a large field of view. The utilization of Tx antenna elements with wider beamwidths will further expand the beam coverage range of the RDA.
During the demonstration, the Tx antenna of the mobile user transmitted an AM pilot signal to the RDA, enabling the establishment of an automatically adaptive communication link between the RDA and the mobile user for video transmission. More importantly, even while the cart was in motion, the video transmission rate remained constant at 36 Mb·s−1, indicating the robustness and stability of the RDA system.
6. Conclusions
This article proposed a highly integrated RDA for two-way communication with automatic beam tracking. The proposed RDA is the first to be implemented using a fully customized CMOS chip. This RDA chip exhibits a sensitivity of −54 dBm and a non-retrodirective signal suppression of 23 dBc, both of which are attributed to the unique design architecture. The performance of the RDA with the CMOS chip was experimentally evaluated, and the results indicated its ability to achieve a ±40° beam coverage within the automatic beam tracking range, accompanied by a 90° 3 dB beamwidth. This article also introduced an easily implementable method to reduce the BPE in conventional RDAs, and the effectiveness of this method was experimentally validated. The total power consumption of the entire RDA is only 0.6 W. The wireless communication demonstration showed that the proposed CMOS RDA offers a promising solution for mobile communication, with improved performance in real-time automatic tracking and beam steering. Moreover, the proposed RDA has the potential to be extended to higher frequency bands.
Acknowledgments
This work was supported in part by the National Key Research and Development Program of China (2019YFB2204701), in part by the National Natural Science Foundation of China (61831006, 62022023, and 62250610223), and in part by the Big Data Computing Center at Southeast University for numerical calculation.
Compliance with ethics guidelines
Jiacheng Guo, Yizhu Shen, Guoqing Dong, Zhuang Han, and Sanming Hu declare that they have no conflict of interest or financial conflicts to disclose.
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