1. Introduction
Traditional computing technologies based on the Von Neumann architecture suffer from limited processing speeds and high power consumption due to the separation of storage and computing functions [1],
[2]. Electrically tunable homojunction devices have been proposed as an effective solution for programmable multifunctional logic [3]. To achieve higher speed and energy efficiency, various approaches for realizing in-memory computing (IMC) technology
[4],
[5] leveraging cutting-edge non-volatile memories have been explored
[6], including resistive random-access memory (RRAM)
[7], phase-change random-access memory (PcRAM)
[8], ferroelectric random-access memory (FeRAM) [9], and magnetic random-access memory (MRAM)
[10]. Among these, MRAM-based devices have attracted significant research interest due to their low operating voltage, high density, fast write times, and high endurance
[11],
[12],
[13]. Over the past decade, IMC technologies based on spin-transfer-torque MRAM (STT-MRAM), including spin-torque majority gates and Boolean logic gates, have been proposed [14],
[15],
[16],
[17],
[18].
Compared to STT-MRAM, spin-orbit torque (SOT) MRAM (SOT-MRAM) provides an efficient approach for constructing IMC devices with near-infinite endurance and reduced power consumption, due to the read–write separation method
[19],
[20]. Recent studies have demonstrated that partial Boolean logic functions can be achieved based on SOT-driven magnetization switching
[21],
[22],
[23],
[24],
[25],
[26],
[27], domain wall motion
[28],
[29],
[30], or skyrmion motion
[31]. Furthermore, several IMC schemes capable of performing electrically controllable complete Boolean logic operations have been reported
[32],
[33],
[34],
[35]. However, implementing logic operations typically requires an additional initialization process for the magnetic tunnel junction (MTJ) or the in-plane magnetic layer.Frequent initialization operations reduce processing speed and increase power consumption in spin-logic devices. Hence, achieving a complete Boolean logic gate without the need for initialization would represent a significant advancement in the practical application of spin-logic devices. In this work, we present a programmable and initialization-free single spin-logic device capable of realizing 16 complete Boolean logic functions. Utilizing in-plane Oersted field generated by an integrated bias field with Au line, deterministic SOT-driven magnetization switching is induced by a sufficiently large in-plane current applied to a heavy metal (HM) layer in the HM/ferromagnet (FM) heterostructure with perpendicular magnetic anisotropy (PMA). A W/CoFeB/MgO heterostructure with PMA was employed in this study. The switching polarity of the heterostructure is controlled by the orientation of the in-plane bias field produced by the currents flowing through the bias-field Au line. By programming the current directions along the Au line and HM layer, we experimentally demonstrated the execution of 16 complete Boolean logic types, allowing logic operations to be performed in one step by simultaneously applying inputs without initialization. This work illustrates the significant potential of spin-logic devices in IMC architectures, surpassing the limitations of traditional Von Neumann computing.
2. Experimental
Sample preparation. A W(5)/CoFeB(1.1)/MgO(2)/Ta(2) heterostructure with thickness in nanometers was deposited on a thermally oxidized Si substrate at room temperature using magnetron sputtering. The thin-film stack was patterned into Hall bars through photolithography and electron beam lithography, followed by argon-ion milling. The channel width of the Hall devices was 1 μm. Atomic layer deposition was utilized to deposit a 50 nm Al2O3 film on the devices at 200 °C. To expose the electrode areas, lithography was used while the remaining areas were covered with photoresist. Argon-ion etching (dry etching) removed approximately 35 nm of Al2O3, and buffered oxide etching, a mixture of HF and NH4F, was used for wet etching of the remaining 15 nm of Al2O3. A Cr (10 nm)/Au (100 nm) bilayer was deposited using electron beam evaporation to create an Au line and cover the electrode with Au. The Au line has a width of 50 µm, while the electrode size is 100 µm × 100 µm.
Electrical measurements. For the measurement of anomalous Hall resistance, currents were applied to the Au line by a direct current (DC) source (Keithley model 2400, Tektronix Inc., USA), while the writing currents were applied to the HM layer of the device by a DC source (Keithley model 6221, Tektronix Inc.) and measured Hall voltage by a nanovoltmeter (Keithley model 2182A, Tektronix Inc.). For each logic operation, the current through the Au line was 0.2 A (corresponding to a current density of ±3.63 MA·cm−2) with a duration of 0.12 s. The writing current applied to the HM layer was 1.8 mA (corresponding to a current density of ±22.2 MA·cm−2) with a duration of 0.02 s. A reading current of 0.05 mA (corresponding to a current density of +0.62 MA·cm−2) was used to measure the anomalous Hall resistance.
3. Results and discussion
3.1. Design of programmable logic gate
The working principle of the spin-logic device is illustrated in
Fig. 1(a). The core of the logic gate consists of an SOT device and an Au line, which is isolated from the SOT device along the vertical direction, functioning similarly to a mathematical operation unit [36]. When currents
IA,
IB, and
IC (corresponding to the current input ports A–C) are applied to the Au line, in-plane Oersted field (
Htot) is generated within the SOT device region. With the assistance of the Oersted field, a current flowing along the HM layer of the SOT device (the current input port D and the corresponding current (
ID)) induces deterministic switching of the FM layer’s magnetization via the SOT effect. Specifically, the Oersted bias field generated at the heterojunction region should be proportional to (
IA +
IB −
IC) according to Biot–Savart’s law, expressed as
Htot =
k(
IA +
IB −
IC), where
k represents the linear coefficient of (
IA +
IB −
IC) with respect to
Htot. Due to the SOT effect, the magnetization direction of the device is ultimately determined by the relative directions of
Htot and
ID. Assuming a negative spin Hall angle for the HM layer, the magnetization prefers the upward state (+
z-direction), when
Htot is parallel to
ID, and the downward state (−
z-direction) if they are antiparallel
[37],
[38]. To discern the magnetization state, the anomalous Hall effect (AHE) resistance (RH) of the SOT device, serving as the logic output, was measured by applying a reading current (
IRE) in the
x-direction and recording the Hall voltage (
VH) in the
y-direction of the FM layer.
Fig. 1(b) demonstrates bipolar switching under four configurations where
ID and
Htot are aligned along either the positive or negative
x-direction. By changing the SOT switching polarity in a clockwise (black curves) or anti-clockwise (red curves) manner and simultaneously controlling the current flows in Au line and the HM layer, the magnetization state of the FM layer is capable of being controlled precisely.
3.2. SOT-induced magnetization switching
The setup of the programmable logic gate device is illustrated in
Fig. 2(a). The SOT device, comprising an HM/FM bilayer, is positioned beneath Au line and insulated by a 50 nm-thick Al
2O
3 layer. The four current input ports are labeled A, B, C, and D. The SOT device is fabricated into a Hall-bar structure based on a stack consisting of W(5)/CoFeB(1.1)/MgO(2)/Ta(2) with thickness in nanometers. The width of the Hall bar is 1 μm. The detailed fabrication process is described in Section 2.
Fig. 2(b) shows the
RH as a function of the out-of-plane (
Hz) and in-plane (
Hx) magnetic fields, demonstrating the device’s strong PMA with a coercive field of 50 Oe and an anisotropy field of 3000 Oe. The two distinct saturated RH values observed in the
RH–
Hz curve differ by approximately 4 Ω, representing the logic states 0 and 1, respectively.
Fig. 2(c) illustrates the SOT-induced magnetization switching under in-plane magnetic field of ±25 Oe, applied using an electromagnet. The critical currents required for switching are approximately ±1.3 mA (corresponding to ±21.1 MA·cm
−2) under these in-plane field conditions. An in-plane bias field can also be generated by currents flowing through the integrated bias-field Au line, which is electrically isolated from and positioned above the SOT device.
Fig. 2(d) shows the SOT-induced switching of
RH under applied currents of
IA = ± 0.2 A (corresponding to ±3.64 MA·cm
−2) through the Au line. When compared to the externally applied magnetic field-assisted SOT-induced switching, the critical currents are approximately identical, indicating that the Oersted field generated by a current of ±0.2 A through the Au line is approximately equivalent to 25 Oe. There is almost no discrepancies on the estimated magnetic field from different methods among the experimental measurements, theoretical calculations, and micromagnetic simulations (see Section S1 in Appendix A for more details).
3.3. Controlling switching polarity by current input ports A–C
The performance of SOT-induced magnetization switching in the Hall-bar device under an in-plane bias field (controlled by current input ports A, B, and C) was analyzed using the current flowing through the HM layer (controlled by current input port D).
Fig. 3(a) shows SOT-induced switching curves for different logical inputs at ports A, B, and C when sweeping
ID. For ports A, B, and C, a current of +0.2 A represents logic 1, and a current of −0.2 A represents logic 0. Depending on the logic values input to ports A, B, and C, multiple electrical signals combine on the Au line, generating diverse in-plane bias field. Deterministic SOT-induced magnetization switching is achieved with the assistance of the in-plane bias field, and the final magnetization state of the device is indicated by the AHE resistance. The two saturated AHE resistance values correspond to the logic operation results of logics 1 and 0, respectively. Given that the critical switching current varies in each switching curve, the amplitude of
ID is set to a relatively high value to ensure deterministic magnetization switching. Specifically, a current of +1.8 mA represents logic 1, and a current of −1.8 mA represents logic 0 for port D. The
RH values obtained at
ID = ±1.8 mA (corresponding to ±22.2 MA·cm
−2) across the various SOT-induced switching curves align with the expected results from the 16 combinations of input logic states, demonstrating the feasibility of performing multiple Boolean logic operations by controlling the different input ports.
We then evaluated the output reliability of the device under the 16 possible input combinations, with each input port set to either logic 0 or 1 (
IA = ±0.2 A,
IB = ±0.2 A,
IC = ±0.2 A, and
ID = ±1.8 mA). This experiment involved performing 1000 consecutive write–read operations for each input combination, during which the
RH values were recorded. The results, shown in
Fig. 3(b), demonstrate that the
RH values consistently remain in either a high or low resistance state, corresponding to the logic output (
R) of 1 or 0, respectively. The high resistance values fall within the range of +1.5 to +2.2 Ω, while the low resistance values are within the range of −1.5 to −2.2 Ω. Notably, there were no instances of operation failure across all 16 combinations, indicating that the spin-logic gate exhibits excellent robustness and repeatability, ensuring reliable implementation of the complete set of 16 Boolean logic operations.
3.4. Implementation of complete 16 Boolean logic functions
Fig. 4(a) summarizes the definitions of logics 0 and 1 for ports A–D and the output. By programming one, two, or three ports as control ports, as shown in
Fig. 4(b), the experimental demonstration of all 16 complete Boolean logic functions is implemented using the single device (see Section S2 in Appendix A for more details). Specifically, if ports C and D are chosen as programming control ports, ports A and B can perform the logic operations such as
R = A˄B(AND),
R = A˅B(OR),
R = ¬A˅¬B(NAND), and
R = ¬A˄¬B(NOR). If ports B and D are selected as control ports, ports A and C can perform logic operations including
R = ¬A˄C,
R = A˅¬C,
R = ¬A˄C, and
R = A˅¬C. When ports B and C are designated as control ports,
R = A↔D(XNOR) operations can be carried out on ports A and D. If ports A and B are selected as control ports,
R = C⊕D(XOR) operations can be performed on ports C and D. When only port D is chosen as the control port, ports A or B can realize
R = A/B(transfer) and
R = ¬A/¬B(NOT) logic operations. Finally, if ports A, B, and D are designated as programming control ports,
R = 1 (identity) or
R = 0 (null) operations can be performed on port C.
To clarify the implementation process, we use
R = ¬A˅¬B and
R = ¬A˄¬B logic functions as examples. For
R = ¬A˅¬B, as shown in
Fig. 4(c), we control C = 1 (
IC = +0.2 A) and D = 0 (
ID = −1.8 mA). If
IA +
IB ≤ 0 A (i.e., A = B = 0 (
IA +
IB −
IC = −0.6 A), A = 0 and B = 1, or A = 1 and B = 0 (
IA +
IB −
IC = −0.2 A)), the total in-plane bias field will be oriented in the −
x direction, resulting in a clockwise switching polarity. Since
ID is negative, the output is
R = 1. Only when A = B = 1 (
IA +
IB −
IC = +0.2 A, corresponding to a field of approximately +25 Oe) will the total in-plane bias field be oriented in the +
x direction, causing an anti-clockwise switching polarity and resulting in
R = 0.
For
R = ¬A˄¬B, as shown in
Fig. 4(d), we control C = 0 (
IC = −0.2 A) and D = 0 (
ID = −1.8 mA). If
IA +
IB ≥ 0 A, that is, A = B = 1 (
IA +
IB −
IC = +0.6 A), A = 0 and B = 1, or A = 1 and B = 0 (
IA +
IB −
IC = +0.2 A), the total in-plane bias field will be oriented in the +
x direction, resulting in an anti-clockwise switching polarity. Since
ID is negative, the output is
R = 0. Only when A = B = 0 (
IA +
IB −
IC = −0.2 A, corresponding to a field of approximately −25 Oe) will the total in-plane bias field be oriented in the −
x direction, causing a clockwise switching polarity and resulting in
R = 1. To demonstrate the reproducibility of the logic gate, only five periods of input operations for
R = ¬A˅¬B and
R = ¬A˄¬B are shown, although more than five periods were conducted. Notably, all logic operations were processed without initialization.
The experimental results demonstrate the feasibility of realizing complete spin-logic operations in a single device based on the in-plane bias field generated by currents flowing through an integrated bias-field line, which controls the switching polarity. The area and power consumption of the spin-logic device were evaluated, and the bias field strength corresponding to the distance between the free layer and the Au line was showed (see Section S3
in Appendix A for more details). The results indicate that, the required high current is due to the wide Au line used in this conceptual experiment. By miniaturizing the logic device to the MTJ with utilizing the FinFET which adapted for MRAM [39], the driving current can be lowered down to be capable for practical control transistor, meeting high-speed requirements. By further decreasing the current, we can embed the Au-line under the free layer with SOT layer to make the distance between the free layer and the Au line nearer. Furthermore, based on the SOT-MTJ, complete Boolean logic functions can be achieved with a tunneling magnetoresistive read-out method. Thanks to their similar structure as present SOT-MRAM, it is possible to construct the logics with SOT-MTJ and hence build the logic block. In this configuration, the magnetic layer of the SOT-MTJ can be scaled down to dimensions of 100 nm (length) × 60 nm (width) × 5 nm (thickness), and the Au line can be narrowed to 100 nm (length) × 60 nm (width) × 30 nm (thickness). In this case, according to experimental results from Garello et al. [40], when the SOT current density is ±112 MA·cm
−2, the power consumption can be improved to 99.1 μW, and an energy efficiency of 99.1 fJ with high-speed operation can be realized if the write time approaches 1 ns. These results suggest that when configured as the SOT-MTJ structure, the energy efficiency becomes competitive with other logic gate devices that necessitate initialization.
For practical applications, the cascadability is a crucial factor in integrated circuits. The output of an upper logic gate must be transmitted to the input of the subsequent gate for continued logic operations. We theoretically demonstrated a cascade scheme based on the SOT-MTJ by incorporating auxiliary devices for switch circuits (see Section S4 in Appendix A for more details). Furthermore, the attention must be paid to the tradeoff between the number of device ports and the implementation of multiple functionalities, such as non-volatility, initialization-free operation, and especially programmability. In our case, we use one multi-terminal device to implement such functionalities, which would not deteriorate the integration density of logic gates. On the other hand, to further increase integration density, we proposed an interconnection approach for sharing programming control ports across multiple logic devices effectively to enhance array compactness and logic density (see Section S5 in Appendix A for more details). It should be noted that, the logic device is decided by the combination of the Oersted field and the SOT, which are generated at the cross-point by the currents from HM layer in the x direction and the Au line in the y direction. In other words, the in-plane Oersted fields have very little impact on the unchosen logic gates due to their PMA. For real applications, replacing the Hall-bar structure with the MTJ allows for a larger output voltage, which can be directly used as the input signal for the next gate. Thus, by scaling down the device dimensions, the working currents in both the integrated bias-field Au line and the HM layer are significantly reduced, resulting in lower power and area consumption.
4. Conclusions
In summary, we theoretically and experimentally proposed the concept of an electrically programmable logic gate without initialization based on a W/CoFeB/MgO heterojunction. By regulating the currents through the bias-field Au line positioned above the Hall bar to adjust the in-plane Oersted field, we achieved tunable bipolar switching of the magnetization and complete Boolean logic functions. To validate this concept experimentally, we designed a device featuring an integrated bias-field Au line, electrically isolated from and positioned on top of the Hall bar, which allowed logic operations by applying corresponding currents to four ports simultaneously. The logic gate demonstrated good reliability, repeatability, and reproducibility. This work provides promising prospects for the application of non-volatile spin-logic based on the SOT effect for spin-logic operations in an IMC architecture.
CRediT authorship contribution statement
Jie Lin: Writing – original draft, Validation, Supervision, Software, Resources, Project administration, Methodology, Investigation, Data curation, Conceptualization. Shuai Zhang: Writing – review & editing, Validation, Supervision, Software, Resources, Project administration, Methodology, Investigation, Formal analysis, Conceptualization. Shihao Li: Validation, Supervision, Software. Yan Xu: Software, Methodology, Formal analysis, Conceptualization. Xin Li: Writing – original draft, Visualization, Supervision, Methodology, Investigation, Formal analysis, Conceptualization. Wei Duan: Validation, Data curation, Conceptualization. Jincheng Hou: Validation, Supervision, Software, Methodology. Chenxi Zhou: Validation, Supervision, Software, Methodology. Wei Zhan: Validation, Data curation, Conceptualization. Zhe Guo: Validation, Methodology, Conceptualization. Min Song: Supervision, Methodology, Formal analysis. Xiaofei Yang: Software, Resources, Conceptualization. Yufeng Tian: Resources, Investigation. Xuecheng Zou: Supervision, Methodology, Conceptualization. Dan Feng: Visualization, Methodology, Formal analysis, Conceptualization. Long You: Writing – review & editing, Validation, Supervision, Software, Resources, Project administration, Methodology, Investigation, Formal analysis, Conceptualization.
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgments
This work was supported by the National Science and Technology Major Project (2020AAA0109005), the National Natural Science Foundation of China (62374055, 12327806, 62304083, 62074063, 61821003, 61904060, 61904051, and 61674062), the Interdisciplinary Program of Wuhan National High Magnetic Field Center (WHMFC202119), the Shenzhen Science and Technology Program Award (JCYJ20220818103410022), the Shenzhen Virtual University Park (2021Szvup091), and the Natural Science Foundation of Wuhan (2024040701010049). Shuai Zhang acknowledges support from the China Postdoctoral Science Foundation (2022M721237). We thank Wei Xu in the Center of Optoelectronic Micro & Nano Fabrication and Characterizing Facility, Wuhan National Laboratory for Optoelectronics of Huazhong University of Science and Technology for the support in device fabrication.
Appendix A. Supplementary data
Supplementary data to this article can be found online at
https://doi.org/10.1016/j.eng.2025.03.022.
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