Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network

Biao Wang , Feifeng Huang , Qiancheng Wang , Zhao Chen , Hongbin Chen , Quan Wang , Qiu Shao , Yiqin Chen , Zhengyuan Wu , Bo Feng , Ming Ji , Huigao Duan

Engineering ›› 2026, Vol. 58 ›› Issue (3) : 193 -202.

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Engineering ›› 2026, Vol. 58 ›› Issue (3) :193 -202. DOI: 10.1016/j.eng.2025.10.026
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Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network
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Abstract

The backside power-delivery network (BSPDN) has emerged as a promising solution to address wiring congestion challenges in advanced nodes beyond the 3 nm technology threshold. In this study, we demonstrate a novel ruthenium (Ru)-based nano through-silicon via (n-TSV) interconnection technology fabricated on a silicon-on-insulator (SOI) substrate for BSPDN implementation. After fabricating a scallop-free n-TSV array with a high aspect ratio (10.4:1.0) using an advanced multi-step etching process, pure Ru metallization was achieved with a resistivity of 19.9 μΩ·cm. The double-side interconnection adopts a combination of an extreme wafer-thinning technique (final thickness: 500 nm; total thickness variation: < 15 nm) and a plasma-assisted all-dry revealing process, achieving high-precision n-TSV exposure from the backside of the substrate while preserving sidewall dielectric liner integrity (< 1 nm loss). A dry recess etch of Ru in n-TSVs was first developed, with significant selectivity (Ru-to-liner oxide ratio > 50:1), effectively eliminating the metallic sidewall residues. The further extracted average line resistance of the Ru-filled n-TSVs was as low as 29 Ω·μm-1. Finally, after 100 thermal cycling tests (-40 to 125 °C), the relative resistance change remained below 1%, demonstrating the superior reliability and stability of the Ru-based interconnects in the BSPDN. These advancements establish a robust interconnection solution for achieving energy-efficient three-dimensional integrated circuit architectures.

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Keywords

Ruthenium nano through-silicon via / Wafer thinning / Dual-side electrical testing

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Biao Wang, Feifeng Huang, Qiancheng Wang, Zhao Chen, Hongbin Chen, Quan Wang, Qiu Shao, Yiqin Chen, Zhengyuan Wu, Bo Feng, Ming Ji, Huigao Duan. Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network. Engineering, 2026, 58(3): 193-202 DOI:10.1016/j.eng.2025.10.026

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1. Introduction

The relentless pursuit of transistor scaling has driven the semiconductor industry toward three-dimensional (3D) integrated circuits (ICs), where vertical integration by means of through-silicon vias (TSVs) becomes critical for overcoming interconnection limitations in advanced nodes [1-3]. In particular, backside power-delivery networks (BSPDNs) have emerged as a revolutionary paradigm to alleviate front-side routing congestion, achieve voltage (IR)-drop reduction (where IR denotes the product of current and resistance), and improve power integrity by decoupling power/signal interconnects [4-6]. This architectural revolution imposes unprecedented manufacturing requirements, such as high-aspect-ratio (high-AR) nano through-silicon vias (n-TSVs) with low resistivity and ultra-thinned-wafer handling. These challenges are driving breakthroughs in materials engineering and process integration.

Conventional copper (Cu)-based n-TSV technology presents fundamental challenges in BSPDN implementation [7,8]. The inherent trade-off between barrier layer thickness (essential to prevent Cu diffusion) and via resistance becomes exacerbated at nanoscale dimensions, with barrier/liner combinations occupying over 30% of the via volume in sub-100 nm features [9-11]. Alternative metals such as molybdenum (Mo) have been explored for their potential as barrier-free conductors, yet Mo suffers from oxidation and nitridation vulnerabilities during thermal processing, which degrade interfacial stability [12-15]. Furthermore, Mo deposition via atomic layer deposition (ALD) often requires aggressive precursors (e.g., MoCl5 and MoO2Cl2) that induce substrate corrosion, particularly in silicon-on-insulator (SOI)-based devices with sensitive buried oxide (BOX) layers [16-18].

Ruthenium (Ru) has emerged as a promising alternative with the ability for barrier-less deposition and superior oxidation resistance [19-22]. However, in the implementation of a Ru-based BSPDN through n-TSV interconnection, certain key technical problems must be addressed. First, achieving a void-free Ru filling in n-TSVs (AR > 10:1; critical dimension (CD) ≤ 50 nm) requires high-precision control over both the etching and the metallization processes. Conventional Bosch-type deep reactive ion etching (DRIE) induces scallop-sidewall defects and residual tensile stress, leading to interfacial delamination during thermal cycling [23-25]. A scallop-free and low-roughness etching process is required to achieve a high-AR n-TSV array and subsequent conformal Ru deposition. Second, while existing Ru etching research predominantly focuses on planar metallic films, current techniques fail to achieve a residue-free Ru recess in nanoscale high-AR architectures such as n-TSVs [26,27]. This limitation may lead to metallic sidewall contamination and subsequent process defects during BSPDN integration [28]. Third, concurrent with etching and metallization challenges, a Ru-based BSPDN demands the achievement of a thin silicon (Si) thickness (< 500 nm) with < 10% total thickness variation (TTV), as well as high-precision revealing of n-TSVs on the wafer backside [29]. In order to realize ultra-thinned wafers for BSPDN applications, an embedded etch stop layer (ESL) is required to mitigate TTV [29,30]. Conventional thinning sequences that combine mechanical grinding, chemical mechanical polishing (CMP), and wet etching have fundamental limitations that hinder them from achieving a final thickness below 500 nm with < 10% TTV (the ratio of TTV to thickness); moreover, they introduce surface damage and metallic contamination incompatible with nanoscale interconnects [31,32]. Although Interuniversity Microelectronics Centre (IMEC)’s benchmark process, which employs a 10/20 nm Si0.75Ge0.25 ESL with grinding/in situ CMP, demonstrated a thickness reduction of 3 μm from initial 775 μm wafers, the residual TTV reached approximately 400 nm (13.3% variation) [33]. Furthermore, subsequent wet etching through SiGe ESL to realize the backside revealing of the n-TSV introduces critical reliability risks, such as strain-induced interfacial delamination at the Ru-filled n-TSV/SiGe interfaces due to lattice mismatching [34,35].

Herein, we present an integrated technology booster for BSPDNs that combines Ru-based n-TSV metallization with an all-dry extreme thinning process on an SOI substrate. Void-free Ru-filled n-TSV arrays (CD ≤ 50 nm; AR > 10:1) were obtained through optimized multi-step etching and ALD processes, eliminating conventional barrier stacks while achieving conformal coverage. By using 2 μm BOX in an SOI substrate as an ESL, we developed a sequential thinning technique that combines precision grinding and inductively coupled plasma (ICP) deep Si etching, followed by vapor-phase hydrofluoric acid (HF) removal of the BOX layer. This approach exhibits excellent thinning control, achieving a final Si thickness of 500 nm with a TTV < 15 nm (3% variation) across 200 mm wafers. A plasma-assisted all-dry revealing process was innovated to expose the n-TSVs from the backside of the substrate, with sidewall liner oxide damage below 1 nm. A Ru dry recessing process in n-TSVs, with remarkable selectivity (Ru-to-oxide ratio > 50:1), was developed for the first time, effectively eliminating metallic sidewall residues. The electrical characterization results demonstrated the superior conductivity of the Ru-filled n-TSVs, with an average line resistance of 29 Ω·μm-1 and remarkable stability evidenced by a relative resistance change (ΔRTC/R0, where ΔRTC represents the difference between the resistance after thermal shock cycles and the initial resistance and R0 is the initial resistance before testing) below 1%, even after 100 thermal shock cycles (-40 to 125 °C). These advancements in Ru-based n-TSVs and extreme wafer-thinning processes have established a new interconnection solution for the BSPDN architecture while achieving advanced 3D ICs.

2. Methods

2.1. Model simulation and analysis

Fig. 1(a) depicts a typical BSPDN architecture [36], in which n-TSVs serve as critical interconnection elements. To achieve high-AR n-TSVs, a collaborative sidewall architecture is required that can simultaneously address the competitive constraints of multi-physics fields, including the thermal mechanical stress and compatibility requirements for back-end metallization [37-39]. According to this requirement, a 3D finite-element model was implemented using Sentaurus technology computer-aided design (TCAD) software (Synopsys, USA), with an n-TSV height of 500 nm, a top CD of 50 nm, a sidewall liner oxide thickness of 5 nm, and a pure Ru filling metallization layer, as schematically detailed in Fig. 1(b).

Fig. 1(c) presents the stress simulation results of pure Ru-filled n-TSVs with different sidewall profiles under a thermal loading of 500 °C. A comparative evaluation between a tapered structure (88° sidewall angle, corresponding to the 16 nm bottom CD of the n-TSV) and a vertical structure indicated a 30% reduction in maximum principal stress at the SiO2/Ru bottom interface for the tapered configuration (Figs. 1(c-i) and (c-ii)). This stress relief originates from two synergistic factors: The effective metallization volume is reduced (by 34% when the equivalent top CD of the n-TSV is 50 nm); and the unique properties of pure Ru eliminate the inherent interfacial barrier requirements of traditional Cu metallization [40]. The 500 °C simulation temperature specifically emulates BSPDN integration conditions [41,42], maintaining compatibility with complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) thermal budget constraints.

2.2. Manufacturing process

The key processes for integrating a BSPDN with Ru-filled n-TSVs are shown in Fig. S1 of Section S1 in Appendix A. An 8-inch (1 inch = 2.54 cm) SOI wafer with a top Si layer of 500 nm, a BOX layer of 2 μm, and a total thickness of 725 μm serves as the substrate to enable precise control of the final Si thickness (Fig. S1(a)). Prior to n-TSV patterning, a SiO2 hard mask (HM) with a 200 nm thickness is deposited on the substrate via chemical vapor deposition (Section S2 in Appendix A). It should be noted that the focus of this work is mainly on developing a Ru-based n-TSV dual-sided interconnection technology for BSPDN integration; hence, the transistor formation processes (e.g., fin field-effect transistor (FinFET) architecture) and other frontside/backside fabrication steps are not covered in detail (Figs. S1(a), (c), and (l)).

The n-TSVs are patterned using electron beam lithography (Fig. S2(a) in Appendix A), which enables rapid prototyping. Subsequently, an ICP etching system is used to open the HM and etch the n-TSVs. As mentioned above, a tapered n-TSV configuration was specifically engineered to suppress scalloping defects (which are characteristic of the Bosch etching process) along the sidewalls, while leveraging a sloped profile to increase the uniformity of the insulating layers (SiO2) and the step coverage of the Ru [23-25,38]. An advanced three-step etching process was developed based on fluorine radical (F*)-based gases and oxygen (O2) to achieve nanoscale control of the n-TSV profile. The essence of the plasma anisotropic etching of the tapered n-TSV is to find a balance between F* etching and O2 passivation, so that the sidewall is etched in a controlled manner; moreover, the etching rate of the sidewall should be significantly lower than that of the bottom of the vias. Therefore, pure trifluoromethane (CHF3) gas is first used to open the HM (Fig. S2(b) in Appendix A). By adjusting the ICP power, radio frequency (RF) bias voltage, and chamber pressure, the etched HM is given a smaller sidewall angle (θ1), as illustrated in Fig. S2(b). Next, pure sulfur hexafluoride (SF6) gas is used. Due to the bombardment effect of the F* plasma in the ICP system, the HM and Si in the vertical direction are etched faster, increasing the sidewall angle (θ2) of the HM. At the same time, due to the existence of this angle (θ2), a tapered Si etching profile (α1) is obtained (Fig. S2(c) in Appendix A). Subsequently, mixed SF6/O2 gases are adopted to optimize the verticality of the Si via (α2) by using the SiFOx passivation layer during the etching process (Fig. S2(d) in Appendix A) [24,43]. Detailed etch process parameters are provided in Table S1 of Section S2 in Appendix A.

A 10 nm-thick SiO2 dielectric is deposited on the sidewall of the n-TSVs by means of ALD, ensuring the uniform coverage and structural integrity of the subsequent metallization. This process employs bis(diethylamino)silane (BDEAS) as the Si precursor and ozone (O3) as the reactant, with a deposition temperature of 270 °C. The same ALD reactor is employed for the Ru metallization, using bis(ethylcyclopentadienyl)ruthenium [Ru(EtCp)2] as the metal-organic precursor and O2 as the reactant, operating at 300 °C (detailed parameters are reported in Ref. [44]). The dry recess etching of the Ru is carried out in a Cl2/O2 plasma with a Cl2-to-O2 flow rate ratio of 1:4 (in standard cubic centimeter per minute (sccm), at 500 W ICP power, 100 W RF bias, and 5 mTorr pressure (1 Torr = 133.322 Pa)), achieving a selectivity of 53:1 compared with SiO2. This high selectivity minimizes the damage to the sidewall dielectric layers in the Ru-based n-TSVs. The principle of this etching process lies in the utilization of O2 plasma to convert metal Ru and its oxides (RuO2) into volatile substances (e.g., RuO4). Additionally, chlorine (Cl2) acts as a catalyst to further promote the formation of volatile oxidative chlorination complexes (RuClxOy) [45-47]. Using this approach, a pure Ru-filled n-TSV array was fabricated on the SOI substrate (Fig. S1(b)).

The implementation of Ru-based BSPDN integration relies on the backside reveal of the n-TSVs from the device substrate. This process sequence initiates with the permanent bonding of the device wafer to a carrier wafer, followed by wafer flipping and thinning to enable backside lithography and metallization (Fig. S1(d)). While industrial implementation typically employs SiCN-SiCN fusion bonding to achieve this heterogeneous structure integration [33], the workflow proposed in this work utilizes Cu-Cu metallic thermocompression bonding immediately following the metallization of the Ru within the n-TSVs. This approach leverages the superior adhesion compatibility at the Cu/Ru interface, significantly minimizing the risk of interfacial delamination during subsequent backside wafer-thinning processes [48,49]. The absence of a Ru recess or CMP step prior to the Cu-Cu bonding is intentional and serves two primary purposes. First, the top Cu/Ru layer functions as a conductive interface that is essential for forming a four-probe Kelvin testing structure. This Kelvin configuration enables the accurate extraction of n-TSV resistance, providing a robust assessment of the electrical performance of the Ru-filled n-TSVs in BSPDN applications [29]. Second, retaining the Ru layer prevents Cu migration into the sidewall dielectric layer during the thermocompression (350 ℃) bonding process [50].

The post-bonding process commences with sequential substrate backside thinning. Initial mechanical grinding is used to reduce the wafer thickness to 50 μm through bulk Si removal (Fig. S1(e)), followed by DRIE to precisely expose the 2 μm BOX layer (Fig. S1(f)). The DRIE process employs SF6 plasma at 2700 W ICP power with a gas flow of 900 sccm, demonstrating an exceptional Si/BOX selectivity of 66:1. This dual-stage approach effectively eliminates the mechanical-grinding-induced defects (depth: ≤ 10 μm [51,52]), while ensuring a uniform surface at the BOX interface. Subsequent vapor-phase HF etching achieves controlled removal of the BOX layer, with termination at the backside interface of the top Si (Fig. S1(g)).

To achieve the backside revealing of the Ru-filled n-TSVs, a two-step ICP etching process was developed and optimized (Fig. S1(h)). For primary Si thinning, pure HBr plasma is employed to rapidly remove approximately 200 nm from the initial 500 nm-thick top Si layer, with controlled under-etching relative to the TSV height. Subsequently, a precision etching process with HBr/O2 plasma (153:1 Si/SiO2 selectivity) at an etch rate of 5 nm·s-1 is used to enable sub-10 nm accuracy in terminating at the desired n-TSV revealing height (Fig. S1(i)).

The backside metallization integration commences with the conformal deposition of a 300 nm-thick spin-on-glass (SOG) dielectric layer, achieving a uniform < 5% thickness across the wafer for robust electrical isolation (Fig. S1(j)). A 45°-incident Ar+ ion beam etching (IBE) process is subsequently used to expose the n-TSV structures through the selective removal of the residual SOG and liner oxide, while preserving the sidewall integrity of the Ru (Fig. S1(k)) [53]. Photolithographic patterning with a 200 nm CD enables precise e-beam evaporation of the 20 nm-thick gold (Au) layer, achieving direct contact between the Ru-based TSV and the Au metallization (here, Au is used instead of the subsequent interconnect metal Cu merely to form a metal electrode and extract the line resistance of a single n-TSV). More process details are provided in Sections S2-S5 in Appendix A.

3. Results and discussion

3.1. Manufacturing characterization

Fig. 2 presents scanning electron microscopy (SEM) and transmission electron microscopy (TEM) images of the etched n-TSV array. During the HM etching process, the CHF3 plasma etching exhibits an etch selectivity of approximately 2.7:1.0 between the SiO2 and the photoresist (PR). Due to lateral erosion by the F* and the lack of passivation precursors (e.g., CxFy polymer species) [54], a conical SiO2 profile is formed after etching (Fig. 2(a)). This non-vertical trench geometry, while deviating from conventional anisotropic etching requirements, serves as the foundational step for the subsequent multi-step etching sequences by mitigating the acute stress concentration at the corners and achieving a gradual evolution of the tapered profile through the etching passivation modulation that follows (Fig. S2 in Appendix A).

A two-step Si etching process is subsequently carried out using a predefined geometric template established by the profile of the inclined SiO2 sidewall. Isotropic plasma etching is implemented with pure SF6 to strategically expand the via opening; then, sidewall passivation is achieved through the introduction of controllable O2 for synergistic plasma chemical modulation. This multi-step etching engineering strategy precisely controls the sidewall morphology of the n-TSVs, while suppressing the occurrence of scalloping defects and roughness on the sidewall. Eventually, an n-TSV structure with a top CD of 63 nm, a height (H) of 427 nm, and a corresponding AR of 6.8:1.0 is obtained, as shown in Figs. 2(b)-(d). It should be mentioned that, to make it possible to fabricate an n-TSV with a top CD of 63 nm, the PR pattern after lithography process has a CD of about 70 nm. Furthermore, by reducing the size of the lithography pattern to 50 nm, an n-TSV array with a top CD of 40 nm, a height of 410 nm, and a corresponding AR of 10.2:1.0 can be obtained, as shown in Figs. 2(e)-(h), indicating that this multi-step etching process for n-TSVs has excellent robustness. Different post-etch structural characterization results are listed in Appendix A Table S2, with the data acquired based on the measurement strategy and schematic illustrated in Appendix A Fig. S3.

To examine the conformality of the ALD-Ru films during the metallization of the n-TSVs, a triple-trench substrate with an AR of approximately 9.9, a top CD of about 43 nm, and a sidewall liner oxide of approximately 10 nm was applied (Fig. 3). Continuous and void-free ALD-Ru films with a thickness of about 40 nm were obtained with excellent conformality and 90% step coverage in a high-AR n-TSV array, as confirmed by the TEM cross-sectional view (Fig. 3(a)). This result indicates that the reported process is especially promising for the fabrication of Ru-based n-TSV interconnects. Excellent step coverage for an n-TSV substrate with an even higher AR of approximately 16.1 and a minimum top CD of 25 nm was also confirmed by TEM, as shown in Figs. 3(b) and (c). The uniformity of the liner oxide layer across various top CDs was also evaluated, as detailed in Table S3 of Section S3, where the measurement was performed following the strategy illustrated in Appendix A Fig. S4.

By adopting the Cl2/O2 mixed plasma dry-etching process in an ICP system, the high-precision etching of Ru metal in a high-AR n-TSV was achieved for the first time, as evidenced in Fig. 4. Fig. 4(a) presents top-view SEM images of the n-TSV array after the Ru etch-back, while Fig. 4(b) displays the corresponding cross-sectional TEM analysis. As demonstrated in Figs. 4(b)-(d), the developed process achieved anisotropic recessing in the n-TSVs, with a top CD of 26 nm and a depth of 260 nm from the oxide top. Notably, the etched Ru surface was highly uniform, with no residual Ru observed on the liner oxide sidewalls. Importantly, the sidewalls of the liner oxide remained intact, as shown in Figs. 4(d-i)-(d-iii)), validating the high reliability and selectivity of the process. This breakthrough also establishes a novel Ru planarization approach that circumvents conventional CMP limitations, thereby enabling advanced front-side transistor interconnects.

Figs. 5(a) and (b) present the spectroscopic ellipsometry (RC2D, J.A. Woollam, USA) mapping results (each containing 25 measurement points) characterizing the thickness uniformity of the SOI substrates after backside grinding combined with DRIE and subsequent vapor-phase HF removal of the BOX layer. As evidenced in Fig. 5(a), the implementation of DRIE instead of conventional CMP achieves superior thickness control, with the TTV reduced to approximately 200 nm at the BOX interface. This dry-etching approach effectively mitigates the process-induced defects, including microcracks and surface contamination, that are frequently observed in CMP-based thinning processes, demonstrating improved process robustness. Furthermore, after removal of the BOX layer, the SOI structure exhibits remarkable uniformity, with TTV values as low as about 11 nm in the 500 nm-thick top Si (Fig. 5(b)). TTV measurements across all process stages are provided in Appendix A Table S4.

Table 1 [33] demonstrates the significant advancements of the all-dry thinning sequences developed in this work. The innovative dry-process thinning technique (Figs. S1(e)- (g)) achieves exceptional thickness uniformity in extreme Si thinning scenarios. Notably, the TTV of the 500 nm-thick Si is reduced to below 3% (the ratio of TTV to thickness), representing a critical improvement for advanced 3D IC manufacturing. Unlike conventional approaches, the approach presented in this work preserves the integrity of the ESL (the n-TSVs etched on the front side of the wafer do not punch through the ESL), effectively mitigating the delamination risks at the n-TSV/ESL interface caused by stress accumulation during backside-revealing processes. These results collectively validate the excellent thickness homogeneity in the ultra-thin Si substrate, establishing an alternative process framework for BSPDNs.

Fig. 5(c) demonstrates the backside-revealed characteristics of the n-TSVs fabricated via the all-dry etching process. The optimized hybrid etching sequence combining HBr-based and HBr/O2 plasma treatments (process conditions are provided in Appendix A Table S5) enables precise thinning of the top Si layer to about 190 nm, as shown in Fig. 5(c-i). The controlled etching duration achieves tunable revealing heights of 44 nm (Fig. 5(c-ii)) and 75 nm (Fig. 5(c-iii)), highlighting a control precision of < 10 nm. Notably, the sidewall oxides of the Ru maintain their structural integrity, even at the maximum exposure height of 75 nm. However, due to the enhanced ion bombardment at the top of the Ru-based n-TSVs by means of the plasma crowding effect, selective thinning of the top oxides is observed (thinnest remaining: 1.4 nm, compared with a baseline of 10 nm on the Ru sidewalls), as shown in the EDS diagram inserted in Fig. 5(c-iii). This localized oxide removal facilitates subsequent backside metallization by pre-conditioning the contact interfaces, without compromising the structural stability of the n-TSVs.

Fig. 5(d) depicts the direct contact configuration between the backside Au electrode and the Ru in a revealed n-TSV, establishing a Kelvin test circuit for precise evaluation of the electrical characteristics of the individual n-TSVs. The SOG layer effectively insulates the Au electrode from the thinned Si substrate. Notably, the cross-sectional views in Figs. 5(d-i)-(d-iii) clearly reveal the absence of interfacial oxide residues at the Au/Ru interface. This observation confirms the successful removal of both the SOG and oxide layers from the Ru surface through 45°-incident-angle Ar+ IBE during the back-etching process of the SOG (Figs. S1(j) and (k)).

3.2. Electrical and reliability tests

To determine the resistance of the n-TSVs, the wafers were diced into 20 mm × 20 mm chips. The electrical properties of the n-TSVs were measured using a semiconductor parameter analyzer (FS-Pro 380, Primarius, China). To eliminate the influence of the backside integration processes (e.g., bonding-induced strain) and to systematically evaluate the intrinsic electrical behavior of the Ru-filled n-TSVs, a four-probe Kelvin metrology platform was first implemented on the frontside of the SOI substrate (Fig. S1(b)), as illustrated in Fig. 6(a). This architecture incorporates slit-type n-TSVs (Fig. 6(a)) to integrate the metal (Au) electrodes, as depicted in Appendix A Section S6 Fig. S5. Through this configuration, the line resistance of a single n-TSV can be obtained using Eq. (1), eliminating the effects of the contact resistance between the metal electrodes and the Ru.

$R=\left(V^{+}-V^{-}\right) / I0$

where R is the line resistance, I is the current, V+ is the higher voltage, and V- is the lower voltage. The ALD-grown Ru metallization underwent Cl2/O2 ICP recess etching to achieve inter-TSV isolation, followed by patterning of the Au electrodes. Fig. 6(b) shows the relationship between the electric potentials (V1, V2, V3, and V4 in Fig. S5) at different positions and the current. By using the voltage difference between different test points (e.g., Vx - Vy), the average line resistance of the slit-type n-TSVs with a top CD of 29 nm, height of 340 nm (corresponding to a cross-sectional area of ∼6.8 × 103 nm2), and sidewall oxide layer of 10 nm (Figs. S6(a) and (b)) was further calculated to be 29 Ω·μm-1. Statistical analysis of 48 individual slit-type n-TSVs with a top CD of about 29 nm (Fig. S6(a)) revealed an average line resistance distribution of (29.5 ± 3) Ω·μm-1, as shown in Fig. 6(c), demonstrating about 10% variation and confirming the reliability of the n-TSV process at this size. Fig. 6(d) statistically resolves the dimensional scaling effects on the line resistance distribution in slit-type n-TSVs with various top CDs (e.g., 29, 24, and 18 nm). For the 18 nm CD group, the line resistance spanned 57-95 Ω·μm-1, exhibiting about 2.3 times wider variation in comparison with the 29 nm group. This dispersion escalation stems from process-sensitive scaling challenges: The sub-20 nm lithography introduces CD uniformity fluctuations or the high-AR ALD manifests a thickness variation along the n-TSV height profile, as evidenced by the EDS analysis of the thickness distribution of the liner SiO2 (Figs. S6(b) and S4(b)).

Fig. 6(e) reveals a distinct cross-sectional area dependence of the resistivity in the pure-Ru-filled slit-type n-TSVs, demonstrating a systematic increase from 19.9 to 23.2 μΩ·cm as the conductive cross-section shrinks from 6.8 × 103 to 2.8 × 103 nm2 (the cross-sectional areas of different-sized n-TSVs are summarized in Appendix A Table S6). This scaling behavior originates from the intensification of the grain boundary scattering caused by the dual confinement effect: the electron mean free path limitation in sub-30 nm features and the grain size reduction. The observed 16.6% increase in resistivity confirms the prevalence of surface-scattering mechanisms in the nanoscale Ru interconnects.

The leakage characteristics of the slit-type n-TSV arrays under a 6 V bias were systematically investigated (n-TSV dimensions: top CD, ∼29 nm; height, ∼340 nm; pitch, ∼200 nm; sidewall oxide thickness, ∼10 nm), as illustrated in Figs. 7(a) and (b). The results reveal a moderate increase in leakage current with an extension of the overlap length and an increase in the number of n-TSVs within the array. It is notable that, even for the arrays containing ten dense slit-type n-TSVs with an overlap length of approximately 5 μm (Fig. S7 in Appendix A), the leakage current remains exceptionally low, at < 80 pA, demonstrating strong electrical isolation. A further breakdown characterization (Fig. 7(c)) reveals excellent stability, with the leakage current suppressed below 0.2 nA at a 9 V bias for dual-TSV configuration (5 μm overlap).

Fig. 7(d) presents the electromigration (EM) test results of a slit-type pure Ru n-TSV (top CD: ∼29 nm; height: ∼340 nm; length: ∼200 μm) under accelerated stress conditions (250 °C, 24 MA·cm-2). Statistical analysis of five independent n-TSV samples reveals an average time-to-failure (TTF) of 2.37 h, demonstrating the notable EM resistance of the Ru-based interconnects. Furthermore, the cumulative failure probability under these extreme conditions is systematically quantified in Fig. 7(e), providing critical insights into the statistical reliability of the pure Ru-filled n-TSVs.

Fig. 7(f) presents the temperature-dependent line resistance and leakage stability of the Ru-based n-TSVs under thermal cycling tests (-40 to 125 °C; ramp rate of ∼10 °C·min-1). Each cycle comprises heating from -40 to 125 °C, followed by cooling back to -40 °C, with the parameters recorded every 25 cycles. Remarkably, the line resistance of the Ru n-TSVs exhibit minimal variation (< 1%) even after 100 thermal cycles, while the inter-array leakage currents (Fig. S7) maintain exceptional stability, increasing by less than 18% over the entire test duration. Additionally, verification of the structural stress state (Fig. S8 in Section S7 of Appendix A) shows that high-density n-TSV arrays have a stress intensity as low as 69 MPa, confirming their structural robustness. These results underscore the superior thermo-mechanical robustness and electrical reliability of the proposed Ru interconnect architecture, addressing critical challenges in 3D IC BSPDNs, where thermal cycling resilience and long-term performance retention are paramount for high-density integration.

Fig. 8(a) shows the Kelvin test structure for backside-revealed tapered n-TSVs (Figs. 1(b) and Figs. 5(d)) fabricated through the bonding, extreme wafer thinning, and all-dry revealing processes. Fig. 8(b) presents statistical data from 48 tapered n-TSVs with a height of 340 nm and top CD of approximately 29 nm. The measured resistance demonstrates a distribution of (111.8 ± 16) Ω. The successful implementation of this process flow establishes a viable technical pathway for BSPDN architectures through robust sub-30 nm Ru-based n-TSV fabrication.

4. Conclusions

This work presents an advancement in 3D interconnection technology through the development of a pure-Ru n-TSV fabrication process and an extreme wafer-thinning methodology for a BSPDN on an SOI substrate. The proposed innovative multi-step etching and Ru-ALD technique enables void-free Ru metallization in ultra-high-AR (10.4:1.0) n-TSVs with a CD of 39 nm, achieving exceptional electrical performance (19.9 μΩ·cm resistivity) without conventional barrier layers. The sequential substrate-thinning process, which utilizes 2 μm BOX as an ESL, demonstrates excellent precision, with a final thickness of 500 nm and a TTV below 11 nm across 200 mm SOI wafers. A plasma-assisted dry revealing technique successfully exposes the n-TSVs from the backside of the substrate while preserving the dielectric liner integrity, complemented by the first demonstrated Ru dry-recessing process in n-TSVs, which exhibits a > 50:1 selectivity to the liner oxide with complete elimination of metallic sidewall residues. Comprehensive electrical characterization revealed the robust interconnects (29 Ω·μm-1 line resistance) of the Ru-based n-TSVs in a BSPDN, with outstanding reliability metrics: ultra-low inter-TSV leakage currents of 80 pA at a 6 V bias, adjacent TSV breakdown voltages exceeding 9.3 V, and an exceptional EM resistance sustaining 24 MA·cm-2 at 250 °C for 2.37 h. Thermal cycling tests (-40 to 125 °C) confirmed the remarkable stability, with a resistance variation of < 1% and a leakage fluctuation of < 18%. These synergistic innovations establish a manufacturable pathway for implementing energy-efficient 3D IC architectures, thereby resolving critical nanoscale integration challenges in power-delivery networks through novel material engineering and process optimization strategies.

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