Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network

Biao Wang; Feifeng Huang; Qiancheng Wang; Zhao Chen; Hongbin Chen; Quan Wang; Qiu Shao; Yiqin Chen; Zhengyuan Wu; Bo Feng; Ming Ji; Huigao Duan

doi:10.1016/j.eng.2025.10.026

Engineering ›› DOI: 10.1016/j.eng.2025.10.026

review-article

Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network

Biao Wang ^a^,^b
, Feifeng Huang ^a^,^b
, Qiancheng Wang ^a^,^b
, Zhao Chen ^a^,^b
, Hongbin Chen ^a^,^b
, Quan Wang ^a
, Qiu Shao ^a^,^b
, Yiqin Chen ^a^,^b
, Zhengyuan Wu ^c
, Bo Feng ^a^,^b^,^*
, Ming Ji ^d
, Huigao Duan ^a^,^b

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Abstract

The backside power-delivery network (BSPDN) has emerged as a promising solution to address wiring congestion challenges in advanced nodes beyond the 3 nm technology threshold. In this study, we demonstrate a novel ruthenium (Ru)-based nano through-silicon via (n-TSV) interconnection technology fabricated on a silicon-on-insulator (SOI) substrate for BSPDN implementation. After fabricating a scallop-free n-TSV array with a high aspect ratio (AR) (10.4:1.0) using an advanced multi-step etching process, pure Ru metallization was achieved with a resistivity of 19.9 μΩ·cm. The double-side interconnection adopts a combination of an extreme wafer-thinning technique (final thickness: 500 nm; total thickness variation (TTV): < 15 nm) and a plasma-assisted all-dry revealing process, achieving high-precision n-TSV exposure from the backside of the substrate while preserving sidewall dielectric liner integrity (< 1 nm loss). A dry recess etch of Ru in n-TSVs was first developed, with significant selectivity (Ru-to-liner oxide ratio > 50:1), effectively eliminating the metallic sidewall residues. The further extracted average line resistance of the Ru-filled n-TSVs was as low as 29 Ω·μm⁻¹. Finally, after 100 thermal cycling tests (–40 to 125 °C), the relative resistance change remained below 1%, demonstrating the superior reliability and stability of the Ru-based interconnects in the BSPDN. These advancements establish a robust interconnection solution for achieving energy-efficient three-dimensional integrated circuit architectures.

Keywords

Ruthenium nano through-silicon via / Wafer thinning / Dual-side electrical testing

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Biao Wang, Feifeng Huang, Qiancheng Wang, Zhao Chen, Hongbin Chen, Quan Wang, Qiu Shao, Yiqin Chen, Zhengyuan Wu, Bo Feng, Ming Ji, Huigao Duan. Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network. Engineering DOI:10.1016/j.eng.2025.10.026

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