CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence

Yuxuan Hou , Hehe Fan , Jianrong Zhang , Yue Zhang , Hua Chen , Min Zhou , Faxin Yu , Roger Zimmermann , Yi Yang

Engineering ›› : 202512025

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Engineering ›› :202512025 DOI: 10.1016/j.eng.2025.12.025
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CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence
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Abstract

The automatic synthesis of analog circuits presents significant challenges. Most existing approaches formulate the problem as a single-objective optimization task, overlooking the fact that design specifications for a given circuit type can vary widely across applications. To address this limitation, we introduce specification-conditioned analog circuit generation, a task that directly generates analog circuits based on stated specifications. The motivation is to find an effective method that leverages existing well-designed circuits to improve automation in analog circuit design. Specifically, we propose CktGen, a simple yet effective variational autoencoder model that maps discretized specifications and circuits into a joint latent space and reconstructs the circuit from that latent vector. Notably, as a single specification may correspond to multiple valid circuits, naively fusing the specification information into a generative model does not capture these one-to-many relationships. To address this, we first decouple the encoding process of circuits and specifications and align their mapped latent space. Then, we employ contrastive training with a filter mask to maximize differences between encoded circuits and specifications. Furthermore, classifier guidance along with latent feature alignment promotes the clustering of circuits sharing the same specification, thus avoiding model collapse into trivial one-to-one mappings. By canonicalizing the latent space with respect to the specifications, we can further optimize and search for an optimal circuit that meets the valid target specification. We conduct comprehensive experiments on the open circuit benchmark and introduce several metrics to evaluate cross-model consistency in the specification-conditioned circuit generation task. The experimental results demonstrate that CktGen achieves substantial improvements over existing state-of-the-art methods.

Keywords

Artificial intelligence / Electronic design automation / Circuit generator / Test-time optimization

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Yuxuan Hou, Hehe Fan, Jianrong Zhang, Yue Zhang, Hua Chen, Min Zhou, Faxin Yu, Roger Zimmermann, Yi Yang. CktGen: Automated Analog Circuit Design with Generative Artificial Intelligence. Engineering 202512025 DOI:10.1016/j.eng.2025.12.025

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References

[1]

Gielen GGE, Rutenbar RA. Computer-aided design of analog and mixed-signal integrated circuits. Proc IEEE 2000; 88(12):1825-54.

[2]

Huang G, Hu J, He Y, Liu J, Ma M, Shen Z, et al. Machine learning for electronic design automation: a survey. ACM Trans Des Autom Electron Syst 2021; 26(5):1-46.

[3]

Nikolić B. ML for analog design: good progress, but more to do. In:Proceedings of the 2022 ACM/IEEE Workshop Mach Learn CAD; 2022 Sep 12-13; online. New York City:Association for Computing Machinery; 2022. p. 53-4.

[4]

Sorkhabi SE, Zhang L. Automated topology synthesis of analog and rf integrated circuits: a survey. Integration 2017; 56:128-38.

[5]

Koza JR, Bennett FH, Andre D, Keane MA, Dunlap F. Automated synthesis of analog electrical circuits by means of genetic programming. IEEE Trans Evol Comput 1997; 1(2):109-28.

[6]

Wang H, Wang K, Yang J, Shen L, Sun N, Lee HS, et al. GCN-RL circuit designer:transferable transistor sizing with graph neural networks and reinforcement learning. In:Proceedings of the 57th ACM/IEEE Design Automation Conference (DAC); 2020 Jul 20-24; San Francisco, CA, USA. New York City:Association for Computing Machinery (ACM); 2020. p. 1-6.

[7]

Dong Z, Cao W, Zhang M, Tao D, Chen Y,Zhang X. CktGNN: circuit graph neural network for electronic design automation. 2023. arXiv:2308.16406.

[8]

Torralba A, Chavez J, Franquelo LG. Fasy: a fuzzy-logic based tool for analog synthesis. IEEE Trans Comput Aided Des Integr Circuits Syst 1996; 15(7):705-15.

[9]

Meissner M, Hedrich L. Feats: framework for explorative analog topology synthesis. IEEE Trans Comput Aided Des Integr Circuits Syst 2015; 34(2):213-26.

[10]

Chavez J, Torralba A, Franquelo LG. A fuzzy-logic based tool for topology selection in analog synthesis. Proceedings of the IEEE International Symposium on Circuits and Systems-ISCAS’94; 1994 May 30-Jun 2; London, UK. New York City:IEEE; 1994. p. 367-70.

[11]

Degrauwe MG, Nys O, Dijkstra E, Rijmenants J, Bitz S, Goffart BL, et al. IDAC: an interactive design tool for analog CMOS circuits. IEEE J Solid-State Circuits 1987; 22(6):1106-16.

[12]

Hsu HY, Lin MPH. Automatic analog schematic diagram generation based on building block classification and reinforcement learning. In:editors. In:Proceedings of the 2022 ACM/IEEE Workshop Mach Learn CAD; 2022 Sep 12-13; online. New York City:Association for Computing Machinery (ACM); 2022. p. 43-8.

[13]

Zhao Z, Zhang L. Analog integrated circuit topology synthesis with deep reinforcement learning. IEEE Trans Comput Aided Des Integr Circuits Syst 2022; 41(12):5138-51.

[14]

Chen Z, Meng S, Yang F, Shang L, Zeng X. Total:topology optimization of operational amplifier via reinforcement learning. In:Proceedings of the 2023 24th International Symposium on Quality Electronic Design (ISQED); 2023 Apr 5-7; San Francisco, CA, USA. New York City:IEEE; 2023. p. 1-8.

[15]

Harjani R, Rutenbar RA, Carley LR. Oasys: a framework for analog circuit synthesis. IEEE Trans Comput Aided Des Integr Circuits Syst 1989; 8(12):1247-66.

[16]

Pollie R. Machine learning produces superhuman chip designs. Engineering 2022; 10(3):7-9.

[17]

Zhuang Y, Cai M, Li X, Luo X, Yang Q, Wu F. The next breakthroughs of artificial intelligence: the interdisciplinary nature of AI. Engineering 2020; 6(3):245-7.

[18]

Lyu YG, Wu F. Toward a more general empowering artificial intelligence. Engineering 2023; 25(6):1-2.

[19]

Dastidar TR, Chakrabarti P, Ray PA. Synthesis system for analog circuits based on evolutionary search and topological reuse. IEEE Trans Evol Comput 2005; 9(2):211-24.

[20]

Mattiussi C, Floreano D. Analog genetic encoding for the evolution of circuits and networks. IEEE Trans Evol Comput 2007; 11(5):596-607.

[21]

McConaghy T, Palmers P, Steyaert M, Gielen GG. Trustworthy genetic programming-based synthesis of analog circuit topologies using hierarchical domain-specific building blocks. IEEE Trans Evol Comput 2011; 15(4):557-70.

[22]

Rojec Ž, Bűrmen Á, Fajfar I. Analog circuit topology synthesis by means of evolutionary computation. Eng Appl Artif Intell 2019; 80:48-65.

[23]

Gielen GG, Walscharts HC, Sansen WM. Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE J Solid-State Circuits 1990; 25(3):707-13.

[24]

Vural RA, Yildirim T. 2021 Nov 21-22; Budapest, Hungary. Swarm intelligence based sizing methodology for CMOS operational amplifier. Proceedings of the 2011 IEEE 12th International Symposium on Computational Intelligence and Informatics; New York City:IEEE; 2011. p. 525-8.

[25]

Lu J, Lei L, Yang F, Shang L, Zeng X. 2022 Mar 14-23; Antwerp, Belgium. Topology optimization of operational amplifier in continuous space via graph embedding. Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition; New York City:IEEE; 2022. p. 142-7.

[26]

Lyu W, Yang F, Yan C, Zhou D, Zeng X. Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design. PMLR 2018; 80:3306-14.

[27]

Zhang S, Lyu W, Yang F, Yan C, Zhou D, Zeng X. 2019 Mar 25-29; Florence, Italy. Bayesian optimization approach for analog circuit synthesis using neural network. Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE); New York City:IEEE; 2019. p. 1463-8.

[28]

Li Y, Wang Y, Li Y, Zhou R, Lin Z. An artificial neural network assisted optimization system for analog design space exploration. IEEE Trans Comput Aided Des Integr Circuits Syst 2020; 39(10):2640-53.

[29]

Budak AF, Gandara M, Shi W, Pan DZ, Sun N, Liu B. An efficient analog circuit sizing method based on machine learning assisted global optimization. IEEE Trans Comput Aided Des Integr Circuits Syst 2022; 41(5):1209-21.

[30]

Queipo NV, Haftka RT, Shyy W, Goel T, Vaidyanathan R, Kevin Tucker P. Surrogate-based analysis and optimization. Prog Aerosp Sci 2005; 41(1):1-28.

[31]

Gao T, Yang J, Jiang S, Li Y. An incipient fault diagnosis method based on complex convolutional self-attention autoencoder for analog circuits. IEEE Trans Ind Electron 2024; 71(8):9727-36.

[32]

Gao T, Yang J, Jiang SA. Novel fault detection model based on vector quantization sparse autoencoder for nonlinear complex systems. IEEE Trans Industr Inform 2023; 19(3):2693-704.

[33]

Nye W, Riley DC, Sangiovanni-Vincentelli A, Tits AL. DELIGHT. SPICE: an optimization-based system for the design of integrated circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 1988; 7(4):501-19.

[34]

Gao J, Cao W, Zhang X. RoSE:robust analog circuit parameter optimization with sampling-efficient reinforcement learning. In:Proceedings of the 60th ACM/IEEE Design Automation Conference (DAC); 2023 Jul 9-13; San Francisco, CA, USA. New York City:IEEE; 2023. p. 1-6.

[35]

Antreich K, Eckmueller J, Graeb H, Pronath M, Schenkel F, Schwencker R, et al. WiCkeD:analog circuit synthesis incorporating mismatch. In:Computer-aided design of analog integrated circuits and systems. New York City:Wiley-IEEE Press; 2002. p. 754.

[36]

Zhang M, Jiang S, Cui Z, Garnett R, Chen Y. D-VAE:a variational autoencoder for directed acyclic graphs. In:Proceedings of the 33rd International Conference on Neural Information Processing Systems; 2019 Dec 8-14; Vancouver, BC, Canada. Red Hook: Curran Associates Inc.; 2019. p. 1588-60.

[37]

Fayazi M, Taba MT, Afshari E, Dreslinski R. Angel: fully-automated analog circuit generator using a neural network assisted semi-supervised learning approach. IEEE Trans Circuits Syst I Regul Pap 2023; 70(11):4516-29.

[38]

Lu J, Lei L, Huang J, Yang F, Shang L, Zeng X. Automatic op-amp generation from specification to layout. IEEE Trans Comput Aided Des Integrated Circ Syst 2023; 42(12):4378-90.

[39]

Silveira F, Flandre D, Jespers PG. A gm / ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE J Solid-State Circuits 1996; 31(9):1314-9.

[40]

Chen H, Liu M, Xu B, Zhu K, Tang X, Li S, et al. MAGICAL: an open-source fully automated analog IC layout system from netlist to GDSII. IEEE Des Test 2021; 38(2):19-26.

[41]

Lyu W, Yang F, Yan C, Zhou D, Zeng X. 2018 Jun 24-28; Multi-objective Bayesian optimization for analog/RF circuit synthesis. Proceedings of the 55th ACM/ESDA/IEEE Design Automation Conference (DAC); San Francisco, CA, USA. New York City:IEEE; 2018. p. 1-6.

[42]

Cao W, Benosman M, Zhang X, Ma R. Domain knowledge-based automated analog circuit design with deep reinforcement learning. 2022. arXiv.2202.13185.

[43]

Chen Z, Meng S, Yang F, Shang L, Zeng X. MACRO:Multi-agent reinforcement learning-based cross-layer optimization of operational amplifier. In:Proceedings of the 2024 29th Asia and South Pacific Design Automation Conference; 2024 Jan 22-25; Incheon, Republic of Korea. New York City:IEEE; 2024. p. 423-8.

[44]

Kingma DP, Welling M. Auto-encoding variational Bayes. 2013. arXiv.1312.6114.

[45]

van den Oord A, Li Y, Vinyals O. Representation learning with contrastive predictive coding. 2018. arXiv.1807.03748.

[46]

Chen T, Kornblith S, Swersky K, Norouzi M, Hinton GE. Big self-supervised models are strong semi-supervised learners. Adv Neural Inf Process Syst 2020; 332:2243-55.

[47]

Chen X, Fan H, Girshick R, He K. Improved baselines with momentum contrastive learning. 2020. arXiv.2003.04297.

[48]

Zhang J, Wu T, Ding C, Zhao H, Guo G. Region-level contrastive and consistency learning for semi-supervised semantic segmentation. 2022. arXiv.2204.13314.

[49]

Xu K, Hu W, Leskovec J,Jegelka S. How powerful are graph neural networks? 2018. arXiv:1810.00826.

[50]

Kipf TN,Welling M. Semi-supervised classification with graph convolutional networks. 2016. arXiv:1609.02907.

[51]

Petrovich M, Black MJ,Varol G. TEMOS: generating diverse human motions from textual descriptions. 2022. arXiv:2204.14109.

[52]

Vaswani A, Shazeer N, Parmar N, Uszkoreit J, Jones L, Gomez AN, et al.Attention is all you need. In:Proceedings of the 31st International Conference on Neural Information Processing Systems; 2017 Dec 4-9; Long Beach, CA, USA. Red Hook:Curran Associates Inc.; 2017. p. 6000-10.

[53]

Dong Z, Zhang M, Li F,Chen Y. PACE: a parallelizable computation encoder for directed acyclic graphs. 2022. arXiv:2203.10304.

[54]

Bao J, Chen D, Wen F, et al. CVAE-GAN: fine-grained image generation through asymmetric training. Proc IEEE Int Conf Comput Vision 2017;2745-54.

[55]

Peebles W, Xie S. Scalable diffusion models with transformers. Proc IEEE/CVF Int Conf Comput Vision 2023;4195-205.

[56]

Loshchilov I,Hutter F. Decoupled weight decay regularization. 2017. arXiv:1711.05101.

[57]

Zhang J, Zhang Y, Cun X, Zhang Y, Zhao H, Lu H, et al. 2023 Jun 17-24; Vancouver BC, Canada. Generating human motion from textual descriptions with discrete representations. Proceedings of the 2023 IEEE/CVF Conference on Computer Vision and Pattern Recognition; New York City:IEEE; 2023. p. 14730-40.

[58]

Heusel M, Ramsauer H, Unterthiner T, Nessler B, Hochreiter S.GANS trained by a two time-scale update rule converge to a local nash equilibrium. In:Proceedings of the 31st International Conference on Neural Information Processing Systems; 2017 Dec 4-9; Long Beach, CA, USA. Red Hook:Curran Associates Inc.; 2017. p. 6629-40.

[59]

Poddar S, Oh Y, Lai Y, Zhu H, Hwang B,Pan DZ. INSIGHT: universal neural simulator for analog circuits harnessing autoregressive transformers. 2024. arXiv:2407.07346.

[60]

Vijayaraghavan P, Shi L, Degan E, Mukherjee V,Zhang X. AUTOCIRCUIT-RL: reinforcement learning-driven LLM for automated circuit topology generation. 2025. arXiv:2506.03122.

[61]

Kanagal R. LLM-powered EDA log analysis for effective design debugging. Report. Berkeley: University of California, Berkeley; 2025.

[62]

Skelic L, Xu Y, Cox M, Lu W, Yu T,Han R. Circuit: a benchmark for circuit interpretation and reasoning capabilities of LLMs. 2025. arXiv:2502.07980.

[63]

Vungarala D, Alam S, Ghosh A, Angizi S. SPICEPilot:navigating spice code generation and simulation with AI guidance. In:Proceedings of the 2024 IEEE International Conference on Rebooting Computing (ICRC); 2024 Dec 16-17; San Diego, CA, USA. New York City:IEEE; 2024. p. 1-6.

[64]

Lai Y, Lee S, Chen G, Poddar S, Hu M, Pan DZ, et al. AnalogCoder:analog circuit design via training-free code generation. In:Proceedings of the Thirty-Ninth AAAI Conference on Artificial Intelligence and Thirty-Seventh Conference on Innovative Applications of Artificial Intelligence and Fifteenth Symposium on Educational Advances in Artificial Intelligence; 2025 Feb 25-Mar 4; Philadelphia, Pennsylvania. Washington, DC: Association for the Advancement of Artificial Intelligence; 2025. p. 379-87.

[65]

Lai Y, Poddar S, Lee S, Chen G, Hu M, Yu B, et al. AnalogCoder-pro: unifying analog circuit generation and optimization via multi-modal LLMs. 2025. arXiv:2508.02518.

[66]

Chang CC, Shen Y, Fan S, Li J, Zhang S, Cao N, et al. LaMAGIC:language-model-based topology generation for analog integrated circuits. In:Proceedings of the 41st International Conference on Machine Learning; 2024 Jul 21-27; Vienna, Austria. Norfolk: JMLR.org; 2024. p. 6253-62.

[67]

Chang CC, Lin WH, Shen Y, Chen Y, Zhang X. LaMAGIC2:advanced circuit formulations for language model-based analog topology generation. In:Proceedings of the Forty-second International Conference on Machine Learning; 2025 Jul 13-16; Vancouver, BC, Canada. Norfolk: JMLR.org; 2025. p. 7351-60.

[68]

Gao J, Cao W, Yang J,Zhang X. AnalogGenie: a generative engine for automatic discovery of analog circuit topologies. 2025. arXiv:2503.00205.

[69]

Shi Y, Tao Z, Gao Y, Zhou T, Chang C, Wang Y, et al. AMSNET-KG: a netlist dataset for LLM-based AMS circuit auto-design using knowledge graph RAG. ACM Trans Des Autom Electron Syst 2025; 30(6):1-37.

[70]

Bhandari J, Bhat V, He Y, Garg S, Rahmani H,Karri R. Auto-SPICE: leveraging LLMs for dataset creation via automated SPICE netlist extraction from analog circuit diagrams. 2024. arXiv:2411.14299v1.

[71]

Zhang H, Sun S, Lin Y, Wang R,Bian J. AnalogXpert: automating analog topology synthesis by incorporating circuit design expertise into large language models. 2024. arXiv:2412.19824.

[72]

Liu C, Chen W, Peng A, Du Y, Du L,Yang J. AmpAgent: an LLM-based multi-agent system for multi-stage amplifier schematic design from literature for process and performance porting. 2024. arXiv:2409.14739.

[73]

Chen Z, Zhuang J, Shen J, Ke X, Yang X, Zhou M, et al. AnalogSeeker: an open-source foundation language model for analog circuit design. 2025. arXiv:2508.10409.

[74]

Yin Y, Wang Y, Xu B, Li P. ADO-LLM: analog design Bayesian optimization with in-context learning of large language models. In: Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design; 2024 Oct 27-31; New York City, NY, USA. New York City: Association for Computing Machinery (ACM); 2024. p. 1-9.

[75]

Liu C, Olowe EA,Chitnis D. LLM-based ai agent for sizing of analog and mixed signal circuit. 2025. arXiv:2504.11497.

[76]

Chen HC, Wu L, Gao M, Shen L, Zhong J,Xu Y. DOCEDA: automated extraction and design of analog circuits from documents with large language model. 2024. arXiv:2412.05301.

[77]

Matsuo R, Uhlich S, Venkitaraman A, Bonetti A, Hsieh CY, Momeni A, et al. SCHEMATO-an LLM for netlist-to-schematic conversion. 2024. arXiv:2411.13899.

[78]

Hammoud A, Goyal C, Pathen S, Dai A, Li A, Kielian G, et al. Human language to analog layout using GLAYOUT layout automation framework. In:Proceedings of the ACM/IEEE International Symposium on Machine Learning for CAD; 2024 Sep 9-11; Salt Lake City, UT, USA. New York City:Association for Computing Machinery; 2024. p. 1-7.

[79]

Liu B, Zhang H, Gao X, Kong Z, Tang X, Lin Y, et al. LayoutCopilot: an LLM-powered multi-agent collaborative framework for interactive analog layout design. IEEE Trans Comput Aided Des Integr Circuits Syst 2025; 44(8):3126-39.

[80]

Lin Y, Gao X, Zhang H, Wang R, Huang R. 2022 Oct 25-28; Nanjing, China. Intelligent and interactive analog layout design automation. Proceedings of the IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT); New York City:IEEE; 2022. p. 1-4.

[81]

Gao X, Zhang H, Liu M, Shen L, Pan DZ, Lin Y, et al. Interactive analog layout editing with instant placement and routing legalization. IEEE Trans Comput Aided Des Integr Circuits Syst 2023; 42(3):698-711.

[82]

Chen G, Zhu K, Kim S, Zhu H, Lai Y, Yu B, et al. LLM-enhanced Bayesian optimization for efficient analog layout constraint generation. 2024. arXiv:2406.05250.

[83]

ul Islam M, Sami H, Gaillardon PE, Tenace V. France. EDA-aware RTL generation with large language models. Proceedings of the 2025 Design, Automation & Test in Europe Conference (DATE); 2025 Mar 31-Apr 2; Lyon, New York City:IEEE; 2025. p. 1-6.

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