Frontiers of Information Technology & Electronic Engineering
>> 2021,
Volume 22,
Issue 2
doi:
10.1631/FITEE.1900653
A 0.20–2.43 GHz fractional-
华中科技大学光学与电子信息学院，中国武汉市，430074
Received: 2019-11-29
Accepted: 2021-02-01
Available online: 2021-02-01
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Abstract
A 0.20–2.43 GHz fractional- is presented for multi-band wireless communication systems, in which the scheme adopts low voltage-controlled oscillators (VCOs) and a with reduced . VCOs that determine the out-band of a phase-locked loop (PLL) based are optimized using an automatic amplitude control technique and a high-quality factor figure-8-shaped inductor. A CP with a mismatch suppression architecture is proposed to improve the current match of the CP and reduce the PLL phase errors. Theoretical analysis is presented to investigate the influence of the on the output performance of PLLs. Fabricated in a TSMC 0.18-µm CMOS process, the prototype operates from 0.20 to 2.43 GHz. The PLL synthesizer achieves an in-band of −96.8 dBc/Hz and an out-band of −122.8 dBc/Hz at the 2.43-GHz carrier. The root-mean-square jitter is 1.2 ps under the worst case, and the measured reference spurs are less than −65.3 dBc. The current consumption is 15.2 mA and the die occupies 850 µm×920 µm.
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