Content
Frontiers of Information Technology & Electronic Engineering >> 2015, Volume 16, Issue 8 doi: 10.1631/FITEE.1400439
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of lowvoltageSRAMsense amplifier
School of Electronics and Information Engineering, Anhui University, Hefei 230601, China
Abstract
Keywords
Process-variation-robust ; Sense amplifier (SA) ; Replica bit-line (RBL) delay ; Timing variation
Content