Multi-stage dual replica bit-line delay technique for process-variation-robust timing of lowvoltageSRAMsense amplifier

2015年第16卷第8期

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《信息与电子工程前沿（英文）》 >> 2015年第16卷第8期 doi: 10.1631/FITEE.1400439

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of lowvoltageSRAMsense amplifier

School of Electronics and Information Engineering, Anhui University, Hefei 230601, China

发布日期： 2015-09-08

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摘要

A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).

关键词

Process-variation-robust ; Sense amplifier (SA) ; Replica bit-line (RBL) delay ; Timing variation