正文
《信息与电子工程前沿(英文)》 >> 2015年 第16卷 第8期 doi: 10.1631/FITEE.1400439
Multi-stage dual replica bit-line delay technique for process-variation-robust timing of lowvoltageSRAMsense amplifier
School of Electronics and Information Engineering, Anhui University, Hefei 230601, China
摘要
关键词
Process-variation-robust ; Sense amplifier (SA) ; Replica bit-line (RBL) delay ; Timing variation
正文