Amongst all the scientific achievements in the 20th century, no single invention has impacted our lives more profoundly than the transistors, or semiconductors. Since we entered the era of computing in the 1960s, we have witnessed a number of notable transformational shifts such as the transition to personal computers and then mobile era. Today, humanity stands on the brink of another revolution, digital transformation
[1]. As a semiconductor engineer, I would like to share my personal experiences and insights throughout my half-century journey with semiconductors.
1. Beginning of my journey
My journey with semiconductor began at the College of Electrical Engineering, Seoul National University in the Republic of Korea. Upon graduation, most of my classmates kept studying as they went to research institutes or universities, or joined private companies such as Samsung or Goldstar. I liked the dynamic nature of the corporates, and I decided to pursue my dream in the dynamic and vibrant environment. In 1981, I was selected as an industrial scholarship student of Samsung Electronics, and joined semiconductor manufacturing technology team. Despite many challenges, I was fully committed to my dream, and thanks to support of fellow colleagues, I have made it this far as a 47-year veteran semiconductor engineer.
Reflecting on my career, I saw huge potential in semiconductor and believed this is the way I can contribute to humanity for more convenient, and more prosperous world. Since 1970s, the commercialization of high-density and high-speed transistors has played a crucial role in miniaturizing a form factor of an electronic device and improving its performances. Throughout the past 50 years as a semiconductor engineer, many products and technologies come to my mind. Among them, I would like to cherish four contributions—recessed channel array transistor (RCAT) dynamic random access memory (DRAM), three-dimensional (3D) vertical NAND (V-NAND), high-bandwidth memory (HBM), and multi-bridge channel field-effect transistor (MBCFETTM).
2. Key innovative achievements
2.1. RCAT DRAM
Today's state-of-the-art DRAM has tens of billions of memory bits. Each bit consists of one transistor which is called cell array transistor and one capacitor, as illustrated in
Fig. 1.
In early 2000s, DRAM industry faced the scaling limit of planar cell array transistor below 100 nm. This is because it was no longer possible for planar cell array transistor to satisfy off-state leakage current requirement due to severe short-channel effect. Therefore, overcoming this limitation was urgently needed. My colleagues and I had investigated many potential candidates under the constraints of minimal modification of existing processes and least added cost. After much effort, a breakthrough was achieved by recessing channel, forming a U-shaped 3D structure, as shown in
Fig. 1. This U-shape can increase effectively channel length, thus suppressing short-channel effect while maintaining two-dimensional (2D) layout dimension. RCAT was the first mass-produced 3D transistor in silicon industry. The first RCAT successfully integrated 512 megabits (Mb) DRAMs with a gate length of 75 nm and recessed channel depth of 150 nm, exhibiting drastically improved data retention time as well as cell contact resistance
[2]. The modern DRAM cell array transistor is based on RCAT structure with modifications and improvement. Advancement of RCAT DRAM will be pursued even down to 10 nm regime.
I still cherish the moment when my colleagues and I finally solved technological issues such as uniformity and quality of oxide grown along the U-shaped silicon channel which consist of various crystal orientations. Back then, the silicon industry was not ready to accept silicon dioxide grown on different crystal orientations as gate oxide. And finally we presented the success of RCAT DRAM at 2003 very large scale integration (VLSI) technology symposium
[2].
2.2. 3D V-NAND
An NAND Flash is used as mass storage of data so it has been advanced toward ever-increasing storage capacity with always-decreasing bit cost.
In 2010s, the planar NAND based on floating gate faced serious issues related to physical dimension scaling. As minimum feature size scaled down, serious issues occurred such as increased program and erase electric field, unwanted coupling and pronounced interference between adjacent cells, ever-increased leakage current, and decreased process window. So, we concluded that floating gate NAND could not go beyond 20 nm, thus urgently needed to find the right alternatives.
After thorough investigation on right medium for charge storage to replace floating gate, we finally decided that silicon nitride having charge trap site could be the right material because of its many fundamental advantages over floating gate. For instance, charge traps in silicon nitride film are discrete in nature so they are much immune to leakage current. Secondly, silicon nitride film can be thinner than floating gate. Therefore, it is less susceptible to coupling and interference among neighboring cells. Thirdly, charge trap flash (CTF) does not require thick control gate. Thus, the stack height could be much shorter than that of floating gate. CTF technology was developed and applied to NAND in 2006. With all these key features, 3D V-NAND was commercialized and mass produced by Samsung for the first in the world in 2013
[3]. The first 3D V-NAND successfully offered 128 gigabits (Gb) by vertically stacking as many as 24 cell layers, exhibiting up to 10× higher reliability and 2× faster write performance. Since then, CTF 3D V-NAND has been the norm of NAND industry. That was the beginning of new era of 3D memory.
2.3. HBM
To enhance system performance of applications such as artificial intelligence (AI) processing, it is important to increase memory bandwidth. In addition to innovating the memory chip itself, there have been attempts to increase the interconnect speed as well as to increase the number of input/output (I/O). HBM, a 3D-stacked solution based on through-silicon-via (TSV), was adopted as an industry standard by Joint Electron Device Engineering Council in 2013.
In 2015, my colleagues and I developed and mass-produced the cutting-edge product, HBM2
[4]. Four gigabyte (GB) HBM2 successfully provided unprecedented DRAM performance—more than 7× faster speed for high end computing tasks including parallel computing, graphics rendering, and machine learning. It is created by stacking a buffer die at the bottom and four 8 Gb core dies on top of it. These are then vertically interconnected by TSV holes and microbumps. A single 8 Gb HBM2 die contains over 5000 TSV holes, which is more than 36× that of an 8 Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages. At that time, it was mainly used as a substitute for graphic memory, but currently is adopted as a major solution for AI accelerator with huge potential.
2.4. MBCFETTM (gate-all-around (GAA) transistor)
Logic technology had issues originated from its planar structure, but it was superseded by FinFET structure which has a thin vertical fin in the 2010s, as shown in
Fig. 1.
However, in the 2020s, the FinFET structure also faced the limitations in scaling down physical dimensions. To break through the limit of fin field-effect transistor (FinFET), recent research has focused on the GAA structure, as shown in
Fig. 1, where the gate surrounds the channel and its implementation has been accelerated. In fact, we invented MBCFET
TM about 20 years ago, and reported its fabrication with its electrical characteristics in 2003 Institute of Electrical and Electronics Engineers (IEEE) Transactions on Nanotechnology
[5]. Why MBCFET
TM or Nanosheet? Compared to FinFET that has three sides of the channel surrounded by gate electrodes, MBCFET
TM has four sides of channel, enabling better current drivability. And at the same time, the beauty of MBCFET
TM is that in order to further increase current driving capability, we can just simply add more channels layer by layer because driving capability is proportional to the number of channel layers. As of today, 3 nm MBCFET
TM technology is under mass production by Samsung and commercially available for foundry customers. The first-generation 3 nm MBCFET
TM can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16% compared to 5 nm FinFET, while the second-generation 3 nm MBCFET
TM can reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%. Now, MBCFET
TM and its modifications will be considered the most promising candidate for next-generation technology nodes.
3. Future technology evolution
Recently, despite all the promising and bright future of the semiconductor industry, questions remain about the industry’s ability to sustain its miniaturization trajectory due to greater technological challenges. However, we should not feel overwhelmed. Technological challenges are always meant to be broken and overcome by our relentless drive for innovations and ecosystem-wide shared efforts. I would like to discuss future technology evolution for three key pillars of silicon industry such as DRAM, NAND, and Logic
[6].
3.1. DRAM
To continue scaling down DRAM, advancements in cell transistor structure, capacitor and process integration are essential. The cell transistor has evolved from the planar structure to the recessed structure, and now to the buried RCAT structure. In the future, it will be possible to make it even smaller with a vertical cell array structure
[7],
[8], as shown in
Fig. 2. Compared with the buried one, we can separate two contacts for bit-line and storage capacitor, and place each contact out of plane, achieving the smallest unit cell area, 4F
2. Currently, the cell capacitor uses supporters to create a single pillar, but it will evolve into a structure with double pillars stacked in the future. To enable further scaling, I anticipate the structure of DRAM will transit from a 2D planar to a 3D vertically stacked cell structure, stacking bit cells on top of each other, similar to the transition from 2D planar to 3D vertical NAND
[9]. This will significantly reduce electrical interference between cells and dramatically increase memory capacity. However, we should carefully control the leakage current due to floating body effects.
3.2. NAND
3D NAND has achieved high bit density by vertically stacking CTF-based cells. In the 7th generation of 3D NAND, all NAND manufactures implemented over 170 layers by applying a double stack technology, and cell-over-periphery (CoP) technology where peripheral circuits are placed below the cell array, as shown in
Fig. 3. In the future, challenges will be overcome with a multi-stack architecture such as triple-stack, multi-hole, and wafer bonding technology. Currently, 3D NAND cell layers are below 300, but by around 2030, it is expected that it will reach over 1000 layers through innovations in next generation processes and novel materials. Key is scaling the vertical pitch, requiring advanced high aspect ratio contact (HARC) etching process and higher mobility in poly-silicon channel. However, I am quite certain that ever increasing total stack height eventually necessitates novel storage materials such as hafnia-based ferroelectric or transition metal oxide-based resistive materials, and/or advancements in multibit solutions such as 5-bit or higher multi-level cells
[6],
[10].
3.3. Logic
Logic technology has continued to improve with new materials and process innovation. Currently, semiconductor industry is mass-producing 3 nm products with FinFET or MBCFET
TM, but further technological innovations are required to scale down below 2 nm or even 1 nm. To that end, many efforts are underway to go beyond limitations through structural and material innovations. These include 3D stacked FET (3DSFET) which vertically stacks n-channel metal-oxide-semiconductor (nMOS) transistor on top of p-channel metal-oxide-semiconductor (pMOS) transistor or vice-versa, vertical transport FET (VT-FET) which places source/drain contacts out of plane to decouple short channel effects and contact resistance, and 2D channel materials which may have superior characteristics than Si channel, as shown in
Fig. 4 [6],
[11]. In the future, design technology co-optimization (DTCO) can significantly contribute to the miniaturization of logic technology, especially through innovative vertical interconnects for powers and signals using a wafer backside.
4. Engineer’s creed
Lastly, I would like to share my thoughts on the creed of engineers.
First, we must constantly strive for self-innovation. To precisely understand and utilize technology, the insight gained from looking below the surface is of critical importance. So, I want to emphasize the importance of focusing on fundamental values and make relentless efforts to change ourselves, turning challenges into opportunities. Despite nearly 50 years in semiconductor industry, I feel there's still long way to go.
Second, I believe continuous learning is a necessary virtue. Being an expert involves giving your best in any circumstances, upping your skills, and learning ceaselessly. To that end, I continue to spend time learning, and keeping track of the latest papers and reports to always stay current and expand my understanding.
The last one is thorough execution. One of the most cherished moment in my career was succeeding in developing the 1 Mb DRAM almost 40 years ago. This was the moment when my semiconductor life began in earnest. Though, at the time, everyone around us said it was impossible, I made the impossible possible with my colleagues. This engraved the mindset of an engineer into my heart, “Never give-up”, and keep going unless it is physically impossible, and never cease to innovate myself and my products.
5. Semiconductor creating the future
In summary, modern society could not have been realized without electronic devices using semiconductors. Semiconductors will play even more indispensable role in the future society represented by technologies such as AI, autonomous driving, robotics and many other things which are not known yet. As such, it is no exaggeration to say that the prosperous future of humanity depends on semiconductor innovation. Although many challenges lie ahead in future semiconductor evolution, our innovation to overcome them will continue, and the journey is just beginning.
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