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Dynamic analysis, FPGA implementation, and cryptographic application of an autonomous 5D chaotic system Research Articles

Sifeu Takougang Kingni, Karthikeyan Rajagopal, Serdar Çiçek, Ashokkumar Srinivasan, Anitha Karthikeyan,stkingni@gmail.com

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 6,   Pages 809-962 doi: 10.1631/FITEE.1900167

Abstract: Using a field programmable gate array (FPGA), the proposed autonomous 5D system is implemented and the

Keywords： 混沌系统；霍普夫分岔；共存吸引子；偏置增强；FPGA实现；声音加密    

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A New Adaptive Frame Rate Upconversion Algorithm for Scan Rate Conversion and Its FPGA Implementation

Wu Yong,Zhang Guanglie,Zheng Nanning,Zhang Xia

Strategic Study of CAE 2001, Volume 3, Issue 4,   Pages 56-62

Abstract: By using a look-up table that corresponds to the adjustable parameter and employing FPGA, the algorithm

Keywords： scan format conversion     frame rate up-conversion     block-matching     motion compensation    

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Implementation of PRINCE with resource-efficient structures based on FPGAs Research Articles

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 11,   Pages 1505-1516 doi: 10.1631/FITEE.2000688

Abstract: In this era of pervasive computing, low-resource devices have been deployed in various fields. is a designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for . The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, , and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of , the new architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.

Keywords： 轻量级分组密码；现场可编程门阵列（FPGA）；低成本；PRINCE；嵌入式安全    

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Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Personal View

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 4,   Pages 615-628 doi: 10.1631/FITEE.1800681

Abstract: implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA

Keywords： Lightweight cryptography     Internet of Things (IoT)     Embedded security     Encryption     FPGA     Datapath design    

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Dynamic power-gating for leakage power reduction in FPGAs Research Article

Hadi JAHANIRAD,h.jahanirad@uok.ac.ir

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 4,   Pages 582-598 doi: 10.1631/FITEE.2200084

Abstract: The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementingMicroelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software.

Keywords： Field programmable gate array (FPGA)     Leakage power     Power-gating     Transistor-level circuit design    

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A BCH error correction scheme applied to FPGA with embedded memory Research Articles

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 8,   Pages 1127-1139 doi: 10.1631/FITEE.2000323

Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

Keywords： 纠错算法；Bose–Chaudhuri–Hocquenghem（BCH）码；现场可编程门阵列（FPGA）；闪存    

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Fatigue Detecting System Based on TMS320DM642

Geng Lei,Wu Xiaojuan,Peng Zhang

Strategic Study of CAE 2005, Volume 7, Issue 11,   Pages 87-90

Abstract: using SAA7.115 as its capture AD, TMS320DM642 as its core, SAA7105 as its display DA ,is designed, and FPGA

Keywords： TMS320DM642     fatigue detection     DFS     FPGA     OSD    

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Frequency-controlable sine signal based on PWM and its implementation on FPGA

Lianzhen HUANG, Jiangang LI, Dongjun ZHANG

Frontiers of Mechanical Engineering 2012, Volume 7, Issue 3,   Pages 322-328 doi: 10.1007/s11465-012-0312-9

Abstract: generated by the different Pulse-Width Modulation (PWM) signals generated by Field-Programmable Gate Array (FPGAThe method just takes a few FPGA resources and was proved feasible by the theory.

Keywords： Pulse-Width Modulation (PWM)     Field-Programmable Gate Array (FPGA)     frequency controllable    

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Getting to Net-Zero Emissions

Chris Greig

Engineering 2020, Volume 6, Issue 12,   Pages 1341-1342 doi: 10.1016/j.eng.2020.09.005

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Hydrogen for a Net-Zero Carbon World

Nigel P Brandon, James J Brandon

Engineering 2023, Volume 29, Issue 10,   Pages 8-10 doi: 10.1016/j.eng.2023.08.002

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Estimation and Realization Path of Agricultural Resource Values in Fujian Province

Yi Xiaoyan, Huang Xianlei, Yin Changbin, Wang Heng

Strategic Study of CAE 2019, Volume 21, Issue 5,   Pages 137-143 doi: 10.15302/J-SSCAE-2019.05.005

Abstract:

The values of agricultural resources include the economic value from agricultural production and their ecological service value. This paper aims to assess the values of agricultural resources in Fujian Province by using relevant theoretical research models, clarify the process and path of realizing these values, and propose policy recommendations for further improvement. The research results show that the economic value of agriculture in Fujian Province in 2015 was 355.36 billion yuan, while the ecological service value was 1193.95 billion yuan. Within the ecological service value, values for rest service, temperature regulation, gas regulation, soil conservation, water conservation, and biodiversity service were 316.13, 111.92, 74.80, 132.11, 217.81, and 341.18 billion yuan, respectively. The paths for realizing these values in Fujian Province mainly include construction of agricultural product brands; integration of agricultural production, agricultural product processing, and agricultural market service; agro-ecological compensation; and green financial support. To further increase the values of agricultural resources in Fujian Province, financial support should be increased, pollution-free agricultural products and agricultural products with geographical indications should be promoted, agricultural industry integration should be advanced, the agricultural ecological compensation system should be improved, and ecological awareness education and publicity should be boosted.

Keywords： agricultural resources     value estimation     realization path     Fujian Province    

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Health in an Aging World: What Should We Do? Views & Comments

Yu-Mei Wen

Engineering 2016, Volume 2, Issue 1,   Pages 40-43 doi: 10.1016/J.ENG.2016.01.010

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Design and implementation of structural monitoring systems for Xihoumen Bridge (II): Implementations

Liu Zhiqiang,Li Na,Guo Jian,Feng Liangping,Song Gang

Strategic Study of CAE 2010, Volume 12, Issue 7,   Pages 101-106

Abstract:

The structural monitoring system for Xihoumen Bridge is designed and implemented by employing the design method proposed in the paper of Design and Implementation of Structural Monitoring Systems for Xihoumen Bridge (I): Design Method. The general design framework, the design method and implementation of subsystems are examined. The loads and responses of the bridge are analyzed when the structural monitoring system is running and collecting data. The results indicate the structural monitoring system for Xihoumen Bridge is running normally and achieves the desired objectives. The distributed data acquisition and transmission system based on industrial Ethernet is applied and developed well in the bridge structural monitoring system, and can be popularized.

Keywords： bridge     structural monitoring     industrial ethernet     distributed data acquisition and transmission system     system integration    

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Optimizing the Roadmap to Carbon Neutralization with a New Paradigm

Wen Lai Huang, Jinghai Li

Engineering 2021, Volume 7, Issue 12,   Pages 1678-1679 doi: 10.1016/j.eng.2021.09.005

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Realization of an Optimal Dynamic Geodetic Reference Frame in China: Methodology and Applications Article

Pengfei Cheng, Yingyan Cheng, Xiaoming Wang, Suqin Wu, Yantian Xu

Engineering 2020, Volume 6, Issue 8,   Pages 879-897 doi: 10.1016/j.eng.2020.08.004

Abstract:

The China Geodetic Coordinate System 2000 (CGCS2000) has been used for several years as a formal published reference frame. The coordinates of all global navigation satellite system (GNSS) stations in China need to be corrected to align with the CGCS2000 frame. Different strategies can be adopted for the realization of an optimal reference frame. However, different strategies lead to different results, with differences as great as several decimeters when GNSS station coordinates are transformed into CGCS2000-defined coordinates. The two common methods for the coordinate correction of a GNSS station are quasi-stable adjustment under CGCS2000 and plate movement correction, and the differences between their results can be greater than 10 cm. In this study, a statistic method called “supervised clustering”is applied to the selection of GNSS reference stations; a new scheme named “artition spacing” for the grouping of all processed GNSS stations is proposed; and the plate movement correction method is used to correct the coordinates of all GNSS stations from the GNSS epoch to the CGCS2000 epoch. The results from the new partitioning method were found to be significantly better than those from the conventional station-blocking approach. When coordinates from the stations without grouping were used as the standard, the accuracy of all the three-dimensional coordinate components from the new partitioning method was better than 2 mm. The root mean squares (RMSs) of the velocities in the x, y, and z directions resulting from the supervised clustering method were 0.19, 0.45, and 0.32 mm∙a−1, respectively, which were much smaller than the values of 0.92, 0.72, and 0.97 mm∙a−1 that resulted from the conventional approach. In addition, singular spectrum analysis (SSA) was used to model and predict the position nonlinear movements. The modeling accuracies of SSA were better than 3, 2, and 5 mm in the east (E), north (N), and up (U) directions, respectively; and its prediction accuracies were better than 5 mm and 1 cm for the horizontal and vertical domains, respectively.

Keywords： Optimal reference frame realization     China Plate Model     CGCS2000 maintenance     Nonlinear movement modeling    

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Title Author Date Type Operation

Dynamic analysis, FPGA implementation, and cryptographic application of an autonomous 5D chaotic system

Sifeu Takougang Kingni, Karthikeyan Rajagopal, Serdar Çiçek, Ashokkumar Srinivasan, Anitha Karthikeyan,stkingni@gmail.com

Journal Article

A New Adaptive Frame Rate Upconversion Algorithm for Scan Rate Conversion and Its FPGA Implementation

Wu Yong,Zhang Guanglie,Zheng Nanning,Zhang Xia

Journal Article

Implementation of PRINCE with resource-efficient structures based on FPGAs

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Journal Article

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Journal Article

Dynamic power-gating for leakage power reduction in FPGAs

Hadi JAHANIRAD,h.jahanirad@uok.ac.ir

Journal Article

A BCH error correction scheme applied to FPGA with embedded memory

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Journal Article

Fatigue Detecting System Based on TMS320DM642

Geng Lei,Wu Xiaojuan,Peng Zhang

Journal Article

Frequency-controlable sine signal based on PWM and its implementation on FPGA

Lianzhen HUANG, Jiangang LI, Dongjun ZHANG

Journal Article

Getting to Net-Zero Emissions

Chris Greig

Journal Article

Hydrogen for a Net-Zero Carbon World

Nigel P Brandon, James J Brandon

Journal Article

Estimation and Realization Path of Agricultural Resource Values in Fujian Province

Yi Xiaoyan, Huang Xianlei, Yin Changbin, Wang Heng

Journal Article

Health in an Aging World: What Should We Do?

Yu-Mei Wen

Journal Article

Design and implementation of structural monitoring systems for Xihoumen Bridge (II): Implementations

Liu Zhiqiang,Li Na,Guo Jian,Feng Liangping,Song Gang

Journal Article

Optimizing the Roadmap to Carbon Neutralization with a New Paradigm

Wen Lai Huang, Jinghai Li

Journal Article

Realization of an Optimal Dynamic Geodetic Reference Frame in China: Methodology and Applications

Pengfei Cheng, Yingyan Cheng, Xiaoming Wang, Suqin Wu, Yantian Xu

Journal Article