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Implementation of PRINCE with resource-efficient structures based on FPGAs Research Articles

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 11,   Pages 1505-1516 doi: 10.1631/FITEE.2000688

Abstract: In this era of pervasive computing, low-resource devices have been deployed in various fields. is a designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for . The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, , and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of , the new architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.

Keywords： 轻量级分组密码；现场可编程门阵列（FPGA）；低成本；PRINCE；嵌入式安全    

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Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Personal View

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 4,   Pages 615-628 doi: 10.1631/FITEE.1800681

Abstract: implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA

Keywords： Lightweight cryptography     Internet of Things (IoT)     Embedded security     Encryption     FPGA     Datapath design    

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Dynamic power-gating for leakage power reduction in FPGAs Research Article

Hadi JAHANIRAD,h.jahanirad@uok.ac.ir

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 4,   Pages 582-598 doi: 10.1631/FITEE.2200084

Abstract: The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementingMicroelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software.

Keywords： Field programmable gate array (FPGA)     Leakage power     Power-gating     Transistor-level circuit design    

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A BCH error correction scheme applied to FPGA with embedded memory Research Articles

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 8,   Pages 1127-1139 doi: 10.1631/FITEE.2000323

Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

Keywords： 纠错算法；Bose–Chaudhuri–Hocquenghem（BCH）码；现场可编程门阵列（FPGA）；闪存    

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BORON: an ultra-lightweight and low power encryption design for pervasive computing Article

Gaurav BANSOD,Narayan PISHAROTY,Abhijit PATIL

Frontiers of Information Technology & Electronic Engineering 2017, Volume 18, Issue 3,   Pages 317-331 doi: 10.1631/FITEE.1500415

Abstract: We propose an ultra-lightweight, compact, and low power block cipher BORON. BORON is a substitution and permutation based network, which operates on a 64-bit plain text and supports a key length of 128/80 bits. BORON has a compact structure which requires 1939 gate equivalents (GEs) for a 128-bit key and 1626 GEs for an 80-bit key. The BORON cipher includes shift operators, round permutation layers, and XOR operations. Its unique design helps generate a large number of active S-boxes in fewer rounds, which thwarts the linear and differential attacks on the cipher. BORON shows good performance on both hardware and software platforms. BORON consumes less power as compared to the lightweight cipher LED and it has a higher throughput as compared to other existing SP network ciphers. We also present the security analysis of BORON and its performance as an ultra-lightweight compact cipher. BORON is a well-suited cipher design for applications where both a small footprint area and low power dissipation play a crucial role.

Keywords： Lightweight cryptography     SP network     Block cipher     Internet of Things (IoT)     Encryption     Embedded security    

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A Polarization Programmable Antenna Array Article

Dingzhao Chen, Yanhui Liu, Ming Li, Pan Guo, Zhuo Zeng, Jun Hu, Y. Jay Guo

Engineering 2022, Volume 16, Issue 9,   Pages 100-114 doi: 10.1016/j.eng.2022.03.015

Abstract:

Reconfigurable antennas are becoming a major antenna technology for future wireless communications and sensing systems. It is known that, with a single linear polarization (LP) reconfigurable antenna element, a preferred polarization can be produced from a set of multiple polarization states, thus improving the quality of the communication link. This paper presents a new concept of a polarization programmable reconfigurable antenna array that consists of a number of polarization reconfigurable antenna elements with a finite number of possible polarization states. By employing a new optimization strategy and programming the polarization states of all the array elements, we demonstrate that it is possible to realize any desired LP in the vectorial array radiation pattern with accurate control of sidelobe and crosspolarization levels (XPLs), thereby achieving the desired polarization to perfectly match that of the required communications signal. Both numerical and experimental results are provided to prove the concept, and they agree well with each other.

Keywords： 阵列天线     极化可编程天线     可重构天线    

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Novel architectures and security solutions of programmable software-defined networking: a comprehensive survey None

Shen WANG, Jun WU, Wu YANG, Long-hua GUO

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 12,   Pages 1500-1521 doi: 10.1631/FITEE.1800575

Abstract:

Nowadays, cyberspace has become a vital part of social infrastructure. With the rapid development of the scale of networks, applications and services have become enriched, and the bearing function of the underlying network devices (such as switches and routers) has also been extended. To promote the dynamics architecture, high-level security, and high quality of service of the network, control network architecture forward separation is a development trend of the networking technology. Currently, software-defined networking (SDN) is one of the most popular and promising technologies. In SDN, high-level strategies are deployed by the proprietary equipment, which is used to guide the data forwarding of the network equipment. This can reduce many complicated functions of the network equipment and improve the flexibility and operability of the implementation and deployment of new network technologies and protocols. However, this novel networking technology faces novel challenges in term of architecture and security. The aim of this study is to offer a comprehensive review of the state-of-the-art research on novel advances of programmable SDN, and to highlight what has been investigated and what remains to be addressed, particularly, in terms of architecture and security.

Keywords： Software-defined networking (SDN)     Security     Programmable    

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Programmable Adaptive Security Scanning for Networked Microgrids Article

Zimin Jiang, Zefan Tang, Peng Zhang, Yanyuan Qin

Engineering 2021, Volume 7, Issue 8,   Pages 1087-1100 doi: 10.1016/j.eng.2021.06.007

Abstract:

Communication-dependent and software-based distributed energy resources (DERs) are extensively integrated into modern microgrids, providing extensive benefits such as increased distributed controllability, scalability, and observability. However, malicious cyber-attackers can exploit various potential vulnerabilities. In this study, a programmable adaptive security scanning (PASS) approach is presented to protect DER inverters against various power-bot attacks. Specifically, three different types of attacks, namely controller manipulation, replay, and injection attacks, are considered. This approach employs both software-defined networking technique and a novel coordinated detection method capable of enabling programmable and scalable networked microgrids (NMs) in an ultra-resilient, time-saving, and autonomous manner. The coordinated detection method efficiently identifies the location and type of power-bot attacks without disrupting normal NM operations. Extensive simulation results validate the efficacy and practicality of the PASS for securing NMs.

Keywords： Networked microgrids     Programmable adaptive security scanning     Coordinated detection     Software defined networking    

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Non-iterative parameter estimation of the 2R-1Cmodel suitable for low-cost embedded hardware Article

Mitar SIMIĆ, Zdenka BABIĆ, Vladimir RISOJEVIĆ, Goran M. STOJANOVIĆ

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 3,   Pages 476-490 doi: 10.1631/FITEE.1900112

Abstract: Parameter estimation of the 2R-1C model is usually performed using iterative methods that require high-performance processing units. Consequently, there is a strong motivation to develop less time-consuming and more power-efficient parameter estimation methods. Such low-complexity algorithms would be suitable for implementation in portable microcontroller-based devices. In this study, we propose the quadratic interpolation non-iterative parameter estimation (QINIPE) method, based on quadratic interpolation of the imaginary part of the measured impedance, which enables more accurate estimation of the characteristic frequency. The 2R-1C model parameters are subsequently calculated from the real and imaginary parts of the measured impedance using a set of closed-form expressions. Comparative analysis conducted on the impedance data of the 2R-1C model obtained in both simulation and measurements shows that the proposed QINIPE method reduces the number of required measurement points by 80% in comparison with our previously reported non-iterative parameter estimation (NIPE) method, while keeping the relative estimation error to less than 1% for all estimated parameters. Both non-iterative methods are implemented on a microcontroller-based device; the estimation accuracy, RAM, flash memory usage, and execution time are monitored. Experiments show that the QINIPE method slightly increases the execution time by 0.576 ms (about 6.7%), and requires 24% (1.2 KB) more flash memory and just 2.4% (32 bytes) more RAM in comparison to the NIPE method. However, the impedance root mean square errors (RMSEs) of the QINIPE method are decreased to 42.8% (for the real part) and 64.5% (for the imaginary part) of the corresponding RMSEs obtained using the NIPE method. Moreover, we compared the QINIPE and the complex nonlinear least squares (CNLS) estimation of the 2R-1C model parameters. The results obtained show that although the estimation accuracy of the QINIPE is somewhat lower than the estimation accuracy of the CNLS, it is still satisfactory for many practical purposes and its execution time reduces to 145−1 30.

Keywords： 2R-1C model     Embedded systems     Parameter estimation     Non-iterative methods     Quadratic interpolation    

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Correspondence: A low-profile dual-polarization programmable dual-beam scanning antenna array Perspective

Shichao ZHU, Yuanfan NING, Hongbo CHU, Pei XIAO, Gaosheng LI,Gaosheng7070@vip.163.com

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 10,   Pages 1504-1512 doi: 10.1631/FITEE.2300253

Abstract: A low-profile dual-polarization dual-beam scanning antenna array based on holographic control theory is presented in this paper. The radiating elements are ingeniously designed to achieve reconfigurable polarization and modulation of the radiation phase by controlling the state of the PIN diodes integrated on each element. A 72-channel series-parallel equal-amplitude and in-phase feeding network is integrated with the radiating array to achieve low-profile characteristics. The two-dimensional (2D) dynamic and accurate deflection of the beam is achieved by a designed direct current (DC) bias circuit that digitally encodes the antenna array using the single-chip microcontroller. A 2-element subarray and a 6×12 array have been fabricated and the digitally controllable radiation pattern of this antenna system has been experimentally verified. The antenna system can achieve the beam scanning of -30° to 30° with a step-scan of 5° at 11 GHz. The proposed antenna system is characterized by low profile, low cost, easy integration, and accurate beam steering, and holds broad application prospects in radar systems, smart antennas, and other fields.
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Nagle algorithm and its application research in embedded Internet

Wang Baobao,Yu Shiming and Wang Zhenyu

Strategic Study of CAE 2014, Volume 16, Issue 2,   Pages 101-105

Abstract:

The existence of small packets in embedded Internet lead to low bandwidth efficiency and even congestion. The Nagle algorithm was applied by standard transmission control protocol（TCP）protocol to reduce the number of small packets. The paper builds embedded Internet network based on ARM7 32 bits micro control unit（MCU）and personal computer（PC）， analyses the principle and working mechanism of Nagle，and suggests an approach to resolve the temporary“deadlock”created by the interaction between the Nagle algorithm and the delayed ACK policy without modifying the Nagle algorithm through improving sampling frequency or filling the buffer in embedded system. The experimental results indicate that this approach is effective and reliable.

Keywords： Nagle algorithm     deadlock     delayed ACK policy     ARM7     embedded Internet    

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A Review of Recent Developments in “On-Chip” Embedded Cooling Technologies for Heterogeneous Integrated Applications Review

Srikanth Rangarajan, Scott Schiffres, Bahgat Sammakia

Engineering 2023, Volume 26, Issue 7,   Pages 185-197 doi: 10.1016/j.eng.2022.10.019

Abstract:

The electronics packaging community strongly believes that Moore’s law will continue for another few years due to recent technological efforts to build heterogeneously integrated packages. Heterogeneous integration (HI) can be at the chip level (a single chip with multiple hotspots), in multi-chip modules, or in vertically stacked three-dimensional (3D) integrated circuits. Flux values have increased exponentially with a simultaneous reduction in chip size and a significant increase in performance, leading to increased heat dissipation. The electronics industry and the academic research community have examined various solutions to tackle skyrocketing thermal-management challenges. Embedded cooling eliminates most sequential conduction resistance from the chip to the ambient, unlike separable cold plates/heat sinks. Although embedding the cooling solution onto an electronic chip results in a high heat transfer potential, technological risks and complexity are still associated with the implementation of these technologies and with uncertainty regarding which technologies will be adopted. This manuscript discusses recent advances in embedded cooling, fluid selection considerations, and conventional, immersion, and additive manufacturing-based embedded cooling technologies.

Keywords： Electronic cooling     Embedded cooling     Immersion cooling    

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Status quo and outlook of reconfigurable research

Li Yufeng,Qiu Han,Lan Julong

Strategic Study of CAE 2008, Volume 10, Issue 7,   Pages 82-89

Abstract: Run-time reconfiguration (RTR), based on the Field Programmable Gate Array (FPGA), is a new promisingAfter introducing the basic concepts of RTR and the current development of the FPGA, this paper summarizes

Keywords： internet     reconfigurable router     reconfigurable network     programmable hardware    

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An embedded lightweight GUI component library and ergonomics optimization method for industry process monitoring Research Articles

Da-peng TAN, Shu-ting CHEN, Guan-jun BAO, Li-bin ZHANG

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 5,   Pages 604-625 doi: 10.1631/FITEE.1601660

Abstract: Developing an efficient and robust lightweight graphic user interface (GUI) for industry process monitoring is always a challenging task. Current implementation methods for embedded GUI are with the matters of real-time processing and ergonomics performance. To address the issue, an embedded lightweight GUI component library design method based on quasar technology embedded (Qt/E) is proposed. First, an entity-relationship (E-R) model for the GUI library is developed to define the functional framework and data coupling relations. Second, a cross-compilation environment is constructed, and the Qt/E shared library files are tailored to satisfy the requirements of embedded target systems. Third, by using the signal-slot communication interfaces, a message mapping mechanism that does not require a call-back pointer is developed, and the context switching performance is improved. According to the multi-thread method, the parallel task processing capabilities for data collection, calculation, and display are enhanced, and the real-time performance and robustness are guaranteed. Finally, the human-computer interaction process is optimized by a scrolling page method, and the ergonomics performance is verified by the industrial psychology methods. Two numerical cases and five industrial experiments show that the proposed method can increase real-time read-write correction ratios by more than 26% and 29%, compared with Windows-CE-GUI and Android-GUI, respectively. The component library can be tailored to 900 KB and supports 12 hardware platforms. The average session switch time can be controlled within 0.6 s and six key indexes for ergonomics are verified by different industrial applications.

Keywords： Embedded lightweight graphic user interface (GUI)     Quasar technology embedded (Qt/E)     Industry process moni-toring     Multi-thread     Ergonomics performance    

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Design and Developing of the Network Device Driver on Embedded Access Point

Wang Zhili,Hu Aiqun,Song Yubo

Strategic Study of CAE 2005, Volume 7, Issue 10,   Pages 91-94

Abstract:

This paper systematically introduces the main structure of network device driver based on embedded Linux. With the PCMCIA API, the software modules of embedded AP (access point) and the developing course are stressed. The testing results of the network device driver are given at the end of the paper.

Keywords： embedded linux     network device driver     PCMCIA    

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Title Author Date Type Operation

Implementation of PRINCE with resource-efficient structures based on FPGAs

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Journal Article

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Journal Article

Dynamic power-gating for leakage power reduction in FPGAs

Hadi JAHANIRAD,h.jahanirad@uok.ac.ir

Journal Article

A BCH error correction scheme applied to FPGA with embedded memory

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Journal Article

BORON: an ultra-lightweight and low power encryption design for pervasive computing

Gaurav BANSOD,Narayan PISHAROTY,Abhijit PATIL

Journal Article

A Polarization Programmable Antenna Array

Dingzhao Chen, Yanhui Liu, Ming Li, Pan Guo, Zhuo Zeng, Jun Hu, Y. Jay Guo

Journal Article

Novel architectures and security solutions of programmable software-defined networking: a comprehensive survey

Shen WANG, Jun WU, Wu YANG, Long-hua GUO

Journal Article

Programmable Adaptive Security Scanning for Networked Microgrids

Zimin Jiang, Zefan Tang, Peng Zhang, Yanyuan Qin

Journal Article

Non-iterative parameter estimation of the 2R-1Cmodel suitable for low-cost embedded hardware

Mitar SIMIĆ, Zdenka BABIĆ, Vladimir RISOJEVIĆ, Goran M. STOJANOVIĆ

Journal Article

Correspondence: A low-profile dual-polarization programmable dual-beam scanning antenna array

Shichao ZHU, Yuanfan NING, Hongbo CHU, Pei XIAO, Gaosheng LI,Gaosheng7070@vip.163.com

Journal Article

Nagle algorithm and its application research in embedded Internet

Wang Baobao,Yu Shiming and Wang Zhenyu

Journal Article

A Review of Recent Developments in “On-Chip” Embedded Cooling Technologies for Heterogeneous Integrated Applications

Srikanth Rangarajan, Scott Schiffres, Bahgat Sammakia

Journal Article

Status quo and outlook of reconfigurable research

Li Yufeng,Qiu Han,Lan Julong

Journal Article

An embedded lightweight GUI component library and ergonomics optimization method for industry process monitoring

Da-peng TAN, Shu-ting CHEN, Guan-jun BAO, Li-bin ZHANG

Journal Article

Design and Developing of the Network Device Driver on Embedded Access Point

Wang Zhili,Hu Aiqun,Song Yubo

Journal Article