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Journal Article 8

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2023 1

2021 2

2020 2

2012 1

2005 1

2001 1

Keywords

FPGA 2

DFS 1

Datapath design 1

Embedded security 1

Encryption 1

Field programmable gate array (FPGA) 1

Field-Programmable Gate Array (FPGA) 1

Internet of Things (IoT) 1

Leakage power 1

Lightweight cryptography 1

OSD 1

Power-gating 1

Pulse-Width Modulation (PWM) 1

TMS320DM642 1

Transistor-level circuit design 1

block-matching 1

fatigue detection 1

frame rate up-conversion 1

frequency controllable 1

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A New Adaptive Frame Rate Upconversion Algorithm for Scan Rate Conversion and Its FPGA Implementation

Wu Yong,Zhang Guanglie,Zheng Nanning,Zhang Xia

Strategic Study of CAE 2001, Volume 3, Issue 4,   Pages 56-62

Abstract: By using a look-up table that corresponds to the adjustable parameter and employing FPGA, the algorithm

Keywords： scan format conversion     frame rate up-conversion     block-matching     motion compensation    

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Dynamic analysis, FPGA implementation, and cryptographic application of an autonomous 5D chaotic system Research Articles

Sifeu Takougang Kingni, Karthikeyan Rajagopal, Serdar Çiçek, Ashokkumar Srinivasan, Anitha Karthikeyan,stkingni@gmail.com

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 6,   Pages 809-962 doi: 10.1631/FITEE.1900167

Abstract: Using a field programmable gate array (FPGA), the proposed autonomous 5D system is implemented and the

Keywords： 混沌系统；霍普夫分岔；共存吸引子；偏置增强；FPGA实现；声音加密    

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Dynamic power-gating for leakage power reduction in FPGAs Research Article

Hadi JAHANIRAD,h.jahanirad@uok.ac.ir

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 4,   Pages 582-598 doi: 10.1631/FITEE.2200084

Abstract: The proposed low-leakage FPGA architecture is compared with state-of-the-art architectures by implementingMicroelectronics Center of North Carolina (MCNC) benchmark circuits on FPGA-SPICE software.

Keywords： Field programmable gate array (FPGA)     Leakage power     Power-gating     Transistor-level circuit design    

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A BCH error correction scheme applied to FPGA with embedded memory Research Articles

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 8,   Pages 1127-1139 doi: 10.1631/FITEE.2000323

Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

Keywords： 纠错算法；Bose–Chaudhuri–Hocquenghem（BCH）码；现场可编程门阵列（FPGA）；闪存    

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Implementation of PRINCE with resource-efficient structures based on FPGAs Research Articles

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 11,   Pages 1505-1516 doi: 10.1631/FITEE.2000688

Abstract: In this era of pervasive computing, low-resource devices have been deployed in various fields. is a designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for . The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, , and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of , the new architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.

Keywords： 轻量级分组密码；现场可编程门阵列（FPGA）；低成本；PRINCE；嵌入式安全    

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Fatigue Detecting System Based on TMS320DM642

Geng Lei,Wu Xiaojuan,Peng Zhang

Strategic Study of CAE 2005, Volume 7, Issue 11,   Pages 87-90

Abstract: using SAA7.115 as its capture AD, TMS320DM642 as its core, SAA7105 as its display DA ,is designed, and FPGA

Keywords： TMS320DM642     fatigue detection     DFS     FPGA     OSD    

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Frequency-controlable sine signal based on PWM and its implementation on FPGA

Lianzhen HUANG, Jiangang LI, Dongjun ZHANG

Frontiers of Mechanical Engineering 2012, Volume 7, Issue 3,   Pages 322-328 doi: 10.1007/s11465-012-0312-9

Abstract: generated by the different Pulse-Width Modulation (PWM) signals generated by Field-Programmable Gate Array (FPGAThe method just takes a few FPGA resources and was proved feasible by the theory.

Keywords： Pulse-Width Modulation (PWM)     Field-Programmable Gate Array (FPGA)     frequency controllable    

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Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Personal View

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 4,   Pages 615-628 doi: 10.1631/FITEE.1800681

Abstract: implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA

Keywords： Lightweight cryptography     Internet of Things (IoT)     Embedded security     Encryption     FPGA     Datapath design    

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Title Author Date Type Operation

A New Adaptive Frame Rate Upconversion Algorithm for Scan Rate Conversion and Its FPGA Implementation

Wu Yong,Zhang Guanglie,Zheng Nanning,Zhang Xia

Journal Article

Dynamic analysis, FPGA implementation, and cryptographic application of an autonomous 5D chaotic system

Sifeu Takougang Kingni, Karthikeyan Rajagopal, Serdar Çiçek, Ashokkumar Srinivasan, Anitha Karthikeyan,stkingni@gmail.com

Journal Article

Dynamic power-gating for leakage power reduction in FPGAs

Hadi JAHANIRAD,h.jahanirad@uok.ac.ir

Journal Article

A BCH error correction scheme applied to FPGA with embedded memory

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Journal Article

Implementation of PRINCE with resource-efficient structures based on FPGAs

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Journal Article

Fatigue Detecting System Based on TMS320DM642

Geng Lei,Wu Xiaojuan,Peng Zhang

Journal Article

Frequency-controlable sine signal based on PWM and its implementation on FPGA

Lianzhen HUANG, Jiangang LI, Dongjun ZHANG

Journal Article

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Journal Article