Implementation of PRINCE with resource-efficient structures based on FPGAs
Research Articles
Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com
Frontiers of Information Technology & Electronic Engineering
2021,
Volume 22,
Issue 11,
Pages 1505-1516
doi:
10.1631/FITEE.2000688
Abstract:
In this era of pervasive computing, low-resource devices have been deployed in various fields. is a designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for . The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, , and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of , the new architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.
Keywords：
轻量级分组密码；现场可编程门阵列（FPGA）；低成本；PRINCE；嵌入式安全
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