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2021, Volume 22, Issue 4

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Frontiers of Information Technology & Electronic Engineering >> 2021, Volume 22, Issue 4 doi: 10.1631/FITEE.2000510

A 9.8–30.1 GHz CMOS low-noise amplifier with a 3.2-dB noise figure using inductor- and transformer-based

Affiliation(s): Guangdong Provincial Key Laboratory of Millimeter-Wave and Terahertz, School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510641, China; School of Science and Engineering, The Chinese University of Hong Kong, Shenzhen, Shenzhen 518172, China; less

Received: 2020-09-28 Accepted: 2021-04-15 Available online: 2021-04-15
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Abstract

A 9.8–30.1 GHz (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and -based techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm technology, the LNA chip occupies an area of only 0.2 mm and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.

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