2002, Volume 4, Issue 1
Strategic Study of CAE >> 2002, Volume 4, Issue 1
A Fault Location Approach for the Testable Realization of Logic Functions
Department of Physics , South China Normal University, Guangzhou 510631, China
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Abstract
An approach of design for testability(DFT) for logic functions is presented in the paper, which employs AND gates and XOR gates tree to realize the generalized Reed-Muller expression of arbitrary logic functions. The major features of the approach are： 1) The circuits adopting the DPT techniques in the paper are totally fault locatable. 2) The circuits have universal test sets for fault detection, the cardinality of the test sets is (n + 5), where n is equal to the number of input variables in the logic function. A fault location method for the circuits is presented, which can identify all fault equivalence classes in the AND gates, and the faults in XOR gate tree in the circuits.
Keywords
logic functions ; Reed-Muller expressions ; design for testability ; single stuck at fault ; faults location
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References
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