A BCH error correction scheme applied to FPGA with embedded memory

2021, Volume 22, Issue 8

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Frontiers of Information Technology & Electronic Engineering >> 2021, Volume 22, Issue 8 doi: 10.1631/FITEE.2000323

A BCH error correction scheme applied to FPGA with embedded memory

Affiliation(s): National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051, China; Shandong Aerospace Electronic Technology Institute, Yantai 264000, China; less

Received: 2020-07-05 Accepted: 2021-08-17 Available online: 2021-08-17

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Abstract

Given the potential for bit flipping of data on a memory medium, a high-speed parallel Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

Keywords

纠错算法 ; Bose–Chaudhuri–Hocquenghem（BCH）码 ; 现场可编程门阵列（FPGA） ; 闪存

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