2022, Volume 23, Issue 6
Frontiers of Information Technology & Electronic Engineering >> 2022, Volume 23, Issue 6 doi: 10.1631/FITEE.2100432
An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
伊斯兰阿扎德大学设拉子分校电气工程系，伊朗设拉子，71987-74731
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Abstract
We present a new -based Wallace-tree (CBW) 8×8 . The ’s s are implemented with a new hybrid (FA) cell, which is based on the (TG) technique. The proposed FA, TG-based AND gate, and hybrid half adder (HA) generate :3 (4≤≤7) digital s with the ability to save at least 50% area occupation. Simulations by 90 nm technology prove the superiority of the proposed FA and digital s under different conditions over the state-of-the-art designs. By using the proposed cells, the CBW exhibits high driving capability, low power consumption, and high speed. The CBW has a 0.0147 mm die area in a pad. The post-layout extraction proves the accuracy of experimental implementation. An mechanism is proposed, in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW in image processing applications. The peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are calculated as image quality parameters, and the results confirm that the presented CBW can be used as an alternative to designs in the literature.
Keywords
Full adder ; Transmission gate ; Counter ; Multiplier ; Three-dimensional layout ; Image blending
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