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2022 2

2017 1

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Multiplier 3

Full adder 2

Add/sub circuit 1

CNTFET-based design 1

Counter 1

Half adder 1

Image blending 1

Multiple-valued logic (MVL) 1

Quantum-dot cellular automata (QCA) 1

Ripple carry adder (RCA) 1

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An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending Research Articles

Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH

Frontiers of Information Technology & Electronic Engineering 2022, Volume 23, Issue 6,   Pages 950-965 doi: 10.1631/FITEE.2100432

Abstract:

We present a new -based Wallace-tree (CBW) 8×8 . The ‍’‍s s are implemented with a new hybrid (FA) cell, which is based on the (TG) technique. The proposed FA, TG-based AND gate, and hybrid half adder (HA) generate :3 (4≤≤7) digital s with the ability to save at least 50% area occupation. Simulations by 90 nm technology prove the superiority of the proposed FA and digital s under different conditions over the state-of-the-art designs. By using the proposed cells, the CBW exhibits high driving capability, low power consumption, and high speed. The CBW has a 0.0147 mm die area in a pad. The post-layout extraction proves the accuracy of experimental implementation. An mechanism is proposed, in which a direct interface between MATLAB and HSPICE is used to evaluate the presented CBW in image processing applications. The peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are calculated as image quality parameters, and the results confirm that the presented CBW can be used as an alternative to designs in the literature.

Keywords： Full adder     Transmission gate     Counter     Multiplier     Three-dimensional layout     Image blending    

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A novel ternary half adder and multiplier based on carbon nanotube field effect transistors Article

Sepehr TABRIZCHI,Nooshin AZIMI,Keivan NAVI

Frontiers of Information Technology & Electronic Engineering 2017, Volume 18, Issue 3,   Pages 423-433 doi: 10.1631/FITEE.1500366

Abstract: In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic

Keywords： CNTFET-based design     Ternary     Half adder     Multiplier     Multiple-valued logic (MVL)    

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Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits Research Article

Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZADEH, Massoud DOUSTI,p-torkzadeh@srbiau.ac.ir,h.khajehnasir@srbiau.ac.ir,m_dousti@srbiau.ac.ir

Frontiers of Information Technology & Electronic Engineering 2022, Volume 23, Issue 8,   Pages 1264-1276 doi: 10.1631/FITEE.2100287

Abstract: Designing logic circuits using complementary metal-oxide-semiconductor (CMOS) technology at the nano scale has been faced with various challenges recently. Undesirable leakage currents, the short-effect channel, and high energy dissipation are some of the concerns. represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS. The key point of designing arithmetic circuits is based on the structure of a 1-bit . A low-complexity block is beneficial for developing various intricate structures. This paper represents scalable 1-bit QCA structures based on cell interaction. Our proposed s encompass preference aspects of QCA design, such as a low number of cells used, low latency, and small area occupation. Also, the proposed structures have been expanded to larger circuits, including a 4-bit , a 4-bit ripple borrow subtractor (RBS), an , and a 2-bit array . All designs were simulated and verified using QCA Designer-E version 2.2. This tool can estimate the energy dissipation as well as evaluate the performance of the circuits. Simulation results showed that the proposed designs are efficient in complexity, area, latency, cost, and energy dissipation.

Keywords： Quantum-dot cellular automata (QCA)     Full adder     Ripple carry adder (RCA)     Add/sub circuit     Multiplier    

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Title Author Date Type Operation

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

Ayoub SADEGHI, Nabiollah SHIRI, Mahmood RAFIEE, Mahsa TAHGHIGH

Journal Article

A novel ternary half adder and multiplier based on carbon nanotube field effect transistors

Sepehr TABRIZCHI,Nooshin AZIMI,Keivan NAVI

Journal Article

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits

Hamideh KHAJEHNASIR-JAHROMI, Pooya TORKZADEH, Massoud DOUSTI,p-torkzadeh@srbiau.ac.ir,h.khajehnasir@srbiau.ac.ir,m_dousti@srbiau.ac.ir

Journal Article