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Design and analysis of carbon nanotube FET based quaternary full adders Article

Mohammad Hossein MOAIYERI,Shima SEDIGHIANI,Fazel SHARIFI,Keivan NAVI

Frontiers of Information Technology & Electronic Engineering 2016, Volume 17, Issue 10, Pages 1056-1066 doi: 10.1631/FITEE.1500214

Abstract: CMOS binary logic is limited by short channel effects, power density, and interconnection restrictions. The effective solution is non-silicon multiple-valued logic (MVL) computing. This study presents two high-performance quaternary full adder cells based on carbon nanotube field effect transistors (CNTFETs). The proposed designs use the unique properties of CNTFETs such as achieving a desired threshold voltage by adjusting the carbon nanotube diameters and having the same mobility as p-type and n-type devices. The proposed circuits were simulated under various test conditions using the Synopsys HSPICE simulator with the 32 nm Stanford comprehensive CNTFET model. The proposed designs have on average 32% lower delay, 68% average power, 83% energy consumption, and 77% static power compared to current state-of-the-art quaternary full adders. Simulation results indicated that the proposed designs are robust against process, voltage, and temperature variations, and are noise tolerant.

Keywords： Nanoelectronics Carbon nanotube FET Multiple-valued logic Quaternary logic