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Strategic Study of CAE >> 2008, Volume 10, Issue 7

Status quo and outlook of reconfigurable research

National Digital Switching System Engineering & Technological Research Center, Zhengzhou 450002, China

Funding project:“九七三”国家重点基础研究发展计划资助项目(2007CB307102) Received: 2007-04-29 Available online: 2008-07-16 14:31:40.000

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Abstract

Today, with new services and applications blooming on the internet, to enable traditional routers to offer enough capability and speed of upgrade along with these services and applications in time would become even harder than ever. Run-time reconfiguration (RTR), based on the Field Programmable Gate Array (FPGA), is a new promising technology that can configure the partial or total hardware logic resources of a system at run time. Based on the technology, reconfigurable routers can support dynamic reconfiguration of new hardware logic for the new service, while keeping the other services still run properly, hence can provide a new possible solution to the update problem of the traditional routers. After introducing the basic concepts of RTR and the current development of the FPGA, this paper summarizes the past major research efforts with respect to the reconfigurable router, as well as the current work on it. Research directions and open problems are also discussed from the point of view of reconfigurable network.

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References

[ 1 ] MacVicar D, Singh S.Accelerating DTP with reconfigurable com- puting engines [ A] .Proceedings of the 8th International Work- shop on Field -programmable Logic and Applications [ C] .Lec- ture Notes in Computer Science, 1998 , 1482 ( Aug) : 391 -395 link1

[ 2 ] Xilinx _ Corp.Xilinx Development System Reference Guide 8.1i [ M /OL ] .http: //toolbox.xilinx.com /docsan /xilinx8 /books / docs /dev /dev.pdf, Xilinx data sheet, 2007 :113

[ 3 ] Xilinx_Corp.XAPP 290 : Two Flows for Partial Reconfiguration: Module Based or Difference Based [ M /OL] .http: //www.xilinx. com, Sept, 2004

[ 4 ] Hauser J, Wawrzynek J.Garp: a M IPS processor with a reconfigu- rable coprocessor [ A] .In IEEE Symp FPGA's for Custom Compu- ting Machines [ C] .Napa, California, 1997 :16 -21 link1

[ 5 ] Singh H, Lee M H, Lu G, et al.MorphoSys: An integrated reconfigurable architecture [ A ] .Proc NATO System Concepts and Integration [ C] .Monterey, CA, 1998 link1

[ 6 ] Singh H, Lee M H, Lu G, et al.MorphoSys: an integrated recon- figurable system for data -parallel and computation -intensive ap- plications [ J ] . Computers, IEEE Transactions on, 2000 , 49 ( 5 ) : 465 -481 link1

[ 7 ] Lee D C, Midkiff S F.Reconfigurable Routers: a New Paradigm for Switching Device Architecture.http: //www.ccm.ece.vt.edu /papers /, 1998

[ 8 ] Lee D C, Harper S J, Athanas P M, et al.A stream -based reconfigurable router prototype [ A] .Proceedings of the IEEE In- ternational Conference on Communications [ C ] .Vancouver, B C, Jun 1999 link1

[ 9 ] Hadzic I, Smith J M.On -the -fly programmable hardware for networks [ A] .Proceedings of GLOBECOM [ C] .Sydney, NSW, Australia, 1998 link1

[10] Hadzic I, Smith J M.P4 : a platform for FPGA implementation of protocol.Boosters [ A ] .Proc FPL ’ 97 [ C ] .Springer LNCS 1304 , September 1997 :438 -447 link1

[11] Fadishei H, Zamani M S, Sabaei M.A novel reconfigurable hardware architecture for ip address lookup [ A ] . ANCS '05 [ C] .Princeton, New Jersey, USA, 2005

[12] Desai M, Gupta R, Karandikar A, et al.Reconfigurable finite - state machine based IP lookup engine for high -speed router [ J ] . IEEE Journal on Selected Areas in Communications ( JSAC) , 2003 , 21 ( 4 ) : 501 -512 link1

[13] Sangireddy R, Somani A.High -speed IP routing with binary decision diagrams based hardware address lookup engine [ J ] . IEEE Journal on Selected Areas in Communications ( JSAC ) , 2003 , 21 ( 4 ) : 513 -521 link1

[14] Maehle E, Albrecht C, Hagenau R.Dynamically reconfigurable coprocessor for network processors [ A ] .In Work in Progress Session, 29th EUROMICRO Conference and EUROM ICRO Sym- posium on Digital System Design [ C] .Institute of System Sci- ence, University of Linz, Linz, Austria, 2003

[15] Albrecht C, Foag J, Koch R, et al.DynaCORE - a dynamical- ly reconfigurable coprocessor architecture for network processors [ A] .Proc of the 14th Euromicro Conference on Parallel, Dis- tributed and Network -based Processing ( PDP 2006 ) [ C ] . IEEE Computer Society, Montbeliard -Sochaux, France, 2006 : 101 -108 link1

[16] Casado M, Watson G, McKeown N.Reconfigurable Networking Hardware: A Classroom Tool [ M] .Hot Interconnects 13 , Stan- ford, August 2005

[17] Lockwood J W, Naufel N, Turner J S, et al.Reprogrammable network packet processing on the field programmable port extend- er ( FPX) [ A] .ACM International Symposium on Field Pro- grammable Gate Arrays ( FPGA'2001 ) , Monterey, CA, 2001 :87 -93 link1

[18] Lockwood J W.Evolvable internet hardware platforms [ A ] . NASA /DoD Workshop on Evolvable Hardware ( EHW'01 ) [ C] . Long Beach, CA, 2001 :271 -279

[19] Lockwood J W, Turner J S, Taylor D E.Field programmable port extender ( FPX) for distributed routing and queuing [ A] .ACM International Symposium on Field Programmable Gate Arrays ( FPGA'2000 ) [ C] .Monterey, CA, 2000 :137 -144 link1

[20] Lockwood J W.An open platform for development of network pro- cessing modules in reprogrammable hardware [ A] .IEC Design Con 2001 , Paper WB -19 [ C] .Santa Clara, CA, 2001 link1

[21] Braun F, Lockwood J, Waldvogel M.Protocol Wrappers for Lay- ered Network Packet Processing in Reconfigurable Hardware [ S] .IEEE Micro, Volume 22 , Number 3 , 2002 :66 -74

[22] Horta E L, Lockwood J W, Taylor D E, et al.Dynamic hardware plugins in an FPGA with partial run -time reconfiguration [ A] . Design Automation Conference ( DAC) [ C] .New Orleans, LA, 2002 link1

[23] Deering S, Hinden R.Internet Protocol Version 6 ( IPv6 ) Speci- fication [ S] .RFC 2460 , December 1998

[24] Covington G A, Comstock C L G, Levine A A, et al.High speed document clustering in reconifigurable hardware [ A] .16 th An- nual Conference on Field Programmable Logic and Applications ( FPL) [ C] .Madrid, Spain, 2006 :411 -417 link1

[25] Moscola J, Cho Y H, Lockwood J W.A reconfigurable architec- ture for multi -gigabit speed content -based routing [ A] .IEEE Symposium on High Performance Interconnects ( Hot Intercon- nects -14 ) [ C] .Stanford, CA, 2006 :61 -66 link1

[26] Cho Y H, Moscola J, Lockwood J W.Context -free grammar based token tagger in reconfigurable devices [ A] .Proceedings of International Workshop on Data Engineering ( ICDE /SeNS ) [ C] .Atlanta, GA, 2006 link1

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