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基于非易失存储器的细粒度检查点 Article

文喆 张,凯 卢,Mikel LUJAN,小平 王,旭 周

Frontiers of Information Technology & Electronic Engineering 2017, Volume 18, Issue 2,   Pages 220-234 doi: 10.1631/FITEE.1500352

Abstract: 新型非易失存储器提供了高访问速度，大容量，字节访问粒度，以及非易失等特性。这些特性将为容错带来新的机遇。本文提出了基于非易失存储器的细粒度检查点。我们在现有操作系统内核的存储管理模块中加入了针对非易失存储器的管理，同时提供了一个非易失堆以供上层应用进行快速的内存分配和对相关对象（或数据结构）的检查点备份。和传统的基于页面粒度的检查点工作相比，我们的机制可以有效的减少检查点拷贝的数据量，从而更好的利用存储器带宽，提升性能。

Keywords： 非易失存储器；字节访问粒度；非易失堆；细粒度检查点    

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Versionized process based on non-volatile random-access memory for fine-grained fault tolerance None

Wen-zhe ZHANG, Kai LU, Xiao-ping WANG

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 2,   Pages 192-205 doi: 10.1631/FITEE.1601477

Abstract: Non-volatile random-access memory (NVRAM) technology is maturing rapidly and its byte-persistence feature allows the design of new and efficient fault tolerance mechanisms. In this paper we propose the versionized process (VerP), a new process model based on NVRAM that is natively non-volatile and fault tolerant. We introduce an intermediate software layer that allows us to run a process directly on NVRAM and to put all the process states into NVRAM, and then propose a mechanism to versionize all the process data. Each piece of the process data is given a special version number, which increases with the modification of that piece of data. The version number can effectively help us trace the modification of any data and recover it to a consistent state after a system crash. Compared with traditional checkpoint methods, our work can achieve fine-grained fault tolerance at very little cost.

Keywords： Non-volatile memory     Byte-persistence     Versionized process     Version number    

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Zirconia quantum dots for a nonvolatile resistive random access memory device Regular Papers

Xiang-lei HE, Rui-jie TANG, Feng YANG, Mayameen S. KADHIM, Jie-xin WANG, Yuan PU, Dan WANG

Frontiers of Information Technology & Electronic Engineering 2019, Volume 20, Issue 12,   Pages 1698-1705 doi: 10.1631/FITEE.1900363

Abstract: We propose a nonvolatile resistive random access memory device by employing nanodispersion of zirconia (ZrO2) quantum dots (QDs) for the formation of an active layer. The memory devices comprising a typical sandwich structure of Ag (top)/ZrO2 (active layer)/Ti (bottom) are fabricated using a facile spin-coating method. The optimized device exhibits a high resistance state/low resistance state resistance difference (about 10 Ω), a good cycle performance (the number of cycles larger than 100), and a relatively low conversion current (about 1 μA). Atomic force microscopy and scanning electron microscope are used to observe the surface morphology and stacking state of the ZrO2 active layer. Experimental results show that the ZrO2 active layer is stacked compactly and has a low roughness (Ra=4.49 nm) due to the uniform distribution of the ZrO2 QDs. The conductive mechanism of the Ag/ZrO2/Ti device is analyzed and studied, and the conductive filaments of Ag ions and oxygen vacancies are focused on to clarify the resistive switching memory behavior. This study offers a facile approach of memristors for future electronic applications.

Keywords： Zirconia quantum dot     Resistive switching     Memory device     Spin coating    

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Anovel non-volatile memory storage system for I/O-intensive applications None

Wen-bing HAN, Xiao-gang CHEN, Shun-fen LI, Ge-zi LI, Zhi-tang SONG, Da-gang LI, Shi-yan CHEN

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 10,   Pages 1291-1302 doi: 10.1631/FITEE.1700061

Abstract:

The emerging memory technologies, such as phase change memory (PCM), provide chances for highperformance storage of I/O-intensive applications. However, traditional software stack and hardware architecture need to be optimized to enhance I/O efficiency. In addition, narrowing the distance between computation and storage reduces the number of I/O requests and has become a popular research direction. This paper presents a novel PCMbased storage system. It consists of the in-storage processing enabled file system (ISPFS) and the configurable parallel computation fabric in storage, which is called an in-storage processing (ISP) engine. On one hand, ISPFS takes full advantage of non-volatile memory (NVM)’s characteristics, and reduces software overhead and data copies to provide low-latency high-performance random access. On the other hand, ISPFS passes ISP instructions through a command file and invokes the ISP engine to deal with I/O-intensive tasks. Extensive experiments are performed on the prototype system. The results indicate that ISPFS achieves 2 to 10 times throughput compared to EXT4. Our ISP solution also reduces the number of I/O requests by 97% and is 19 times more efficient than software implementation for I/O-intensive applications.

Keywords： In-storage processing     File system     Non-volatile memory (NVM)     Storage system     I/O-intensive applications    

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An efficient wear-leveling-aware multi-grained allocator for persistent memory file systems Research Article

Tao CAI, Pengfei GAO, Dejiao NIU, Yueming MA, Tianle LEI, Jianfei DAI,caitao@ujs.edu.cn,1306943800@qq.com

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 5,   Pages 703-715 doi: 10.1631/FITEE.2200462

Abstract: is an effective way to manage increasingly large file system metadata, but it suffers from low concurrency and lack of optimization for . In this paper, a multilevel hash directory based on lazy expansion is designed to improve the concurrency and efficiency of , and a hash bucket management algorithm based on groups is presented to improve the efficiency of hash key management by reducing the size of the hash bucket, thereby improving the performance of . Meanwhile, a hierarchical storage strategy of for NVM is given to take advantage of dynamic random access memory (DRAM) and NVM. Furthermore, on the basis of the device driver for Intel Optane DC Persistent Memory, the prototype of high-concurrency named NEHASH is implemented. Yahoo cloud serving benchmark (YCSB) is used to test and compare with CCEH, level hashing, and cuckoo hashing. The results show that NEHASH can improve read throughput by up to 16.5% and write throughput by 19.3%.

Keywords： Extendible hashing     Non-volatile memory (NVM)     High concurrency    

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& Research Article

Yitian YANG, Youyou LU,yangyiti22@mails.tsinghua.edu.cn,luyouyou@tsinghua.edu.cn

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 5,   Pages 675-687 doi: 10.1631/FITEE.2200469

Abstract: Emergence of new hardware, including and , has brought new opportunities to design. In this paper, we design and implement a new named NICFS based on and SmartNIC. We divide the into two parts: the front end and the back end. In the front end, data writes are appended to the in a log-structured way, leveraging the fast persistence advantage of . In the back end, the data in logs are fetched, processed, and patched to files in the background, leveraging the processing capacity of SmartNIC. Evaluation results show that NICFS outperforms Ext4 by about 21%/10% and about 19%/50% on large and small reads/writes, respectively.

Keywords： Non-volatile memory     Persistent memory     Data processing unit     Smart network interface card (SmartNIC)     File system    

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Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory Research Article

Sutapa SARKAR, Biplab Kumar SIKDAR, Mousumi SAHA

Frontiers of Information Technology & Electronic Engineering 2022, Volume 23, Issue 7,   Pages 1110-1126 doi: 10.1631/FITEE.2100255

Abstract: This paper presents a group-based dynamic scheme intended for resistive random-access memory (ReRAM). Traditional static random-access memory, dynamic random-access memory, NAND, and NOR flash memory are limited by their scalability, power, package density, and so forth. Next-generation memory types like ReRAMs are considered to have various advantages such as high package density, non-volatility, scalability, and low power consumption, but has been a problem. Unreliable memory operation is caused by permanent stuck-at faults due to extensive use of write- or memory-intensive workloads. An increased number of stuck-at faults also prematurely limit chip lifetime. Therefore, a cellular automaton (CA) based dynamic stuck-at fault-tolerant design is proposed here to combat unreliable cell functioning and variable cell lifetime issues. A scalable, block-level fault diagnosis and recovery scheme is introduced to ensure readable data despite multi-bit stuck-at faults. The scheme is a novel approach because its goal is to remove all the restrictions on the number and nature of stuck-at faults in general fault conditions. The proposed scheme is based on Wolfram's null boundary and periodic boundary CA theory. Various special classes of CAs are introduced for 100% fault tolerance: (SACAs), (TACAs), and (MACAs). The target micro-architectural unit is designed with optimal space overhead.

Keywords： Resistive memory     Cell reliability     Stuck-at fault diagnosis     Single-length-cycle single-attractor cellular automata     Single-length-cycle two-attractor cellular automata     Single-length-cycle multiple-attractor cellular automata    

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Optimization Strategy of MPEG-4 AAC Decoder on a Low-cost SoC

Gao Gugang,Shi Longxing,Pu Hanlai,Zhou Fan

Strategic Study of CAE 2007, Volume 9, Issue 10,   Pages 60-64

Abstract:

This paper proposes software optimization strategies using a low-cost SoC which include float-point to fix-point conversion scheme based on statistical analysis and performance oriented customizing scheme for on-chip memory's capacity,  and presents optimization methodology based on these strategies for computation intensive applications.  the MPEG-4 AAC decoding in real-time is implemented as a case study to illustrate the efficiency of the proposed optimization strategy in both performance and cost.  The strategy and methodology also can be used to optimize other DSP applications.

Keywords： software optimization     SoC     FFC     on-chip memory     AAC    

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A BCH error correction scheme applied to FPGA with embedded memory Research Articles

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 8,   Pages 1127-1139 doi: 10.1631/FITEE.2000323

Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

Keywords： 纠错算法；Bose–Chaudhuri–Hocquenghem（BCH）码；现场可编程门阵列（FPGA）；闪存    

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MyWAL: performance optimization by removing redundant input/output stack in key-value store Research Article

Xiao ZHANG, Mengyu LI, Michael NGULUBE, Yonghao CHEN, Yiping ZHAO,zhangxiao@nwpu.edu.cn,limy@mail.nwpu.edu.cn

Frontiers of Information Technology & Electronic Engineering 2023, Volume 24, Issue 7,   Pages 980-993 doi: 10.1631/FITEE.2200496

Abstract: Based on a , the key-value (KV) storage system can provide high reading performance and optimize random writing performance. It is widely used in modern data storage systems like e-commerce, online analytics, and real-time communication. An LSM tree stores new KV data in the memory and flushes to disk in batches. To prevent data loss in memory if there is an unexpected crash, RocksDB appends updating data in the before updating the memory. However, synchronous WAL significantly reduces writing performance. In this paper, we present a new WAL mechanism named MyWAL. It directly manages raw devices (or partitions) instead of saving data on a traditional file system. These can avoid useless metadata updating and write data sequentially on disks. Experimental results show that MyWAL can significantly improve the data writing performance of RocksDB compared to the traditional WAL for small KV data on solid-state disks (SSDs), as much as five to eight times faster. On non-volatile memory express soild-state drives (NVMe SSDs) and , MyWAL can improve data writing performance by 10%‍–‍30%. Furthermore, the results of YCSB (Yahoo! Cloud Serving Benchmark) show that the latency decreased by 50% compared with SpanDB.

Keywords： Key-value (KV) store     Log-structured merge (LSM) tree     Non-volatile memory (NVM)     Non-volatile memory express soild-state drive (NVMe SSD)     Write-ahead log (WAL)    

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Research on Urban Mining Development in China

Sun Xiaofei,Qian Yi,Wen Zongguo,Liu Lili,Shan Guijuan and Li Jinhui

Strategic Study of CAE 2017, Volume 19, Issue 4,   Pages 97-102 doi: 10.15302/J-SSCAE-2017.04.015

Abstract:

China is experiencing a serious shortage of certain mineral reserves, and several important mineral resources are increasingly supplied via foreign imports. This paper proposes urban mining as a promising means of conserving resources and facilitating sustainable economic growth. The author summarizes the origin and meaning of urban mining, and analyzes the development of the ten main types of urban mining in China from 2006 to 2016, which include: scrap iron and steel, scrap non-ferrous metals, electronic waste, and end-of-life vehicles. Next, the author predicts the resource development and utilization potential of urban mining, and evaluates the contribution of urban mining to resource conservation, environmental protection, carbon emissions reduction, and economic development. Based on these analyses, the author presents strategic and policy suggestions to promote urban mining development in China.

Keywords： urban mining     circular economy     resource conservation potential     scenario analysis    

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A review of computer graphics approaches to urban modeling from a machine learning perspective Review Article

Tian Feng, Feiyi Fan, Tomasz Bednarz,t.feng@latrobe.edu.au

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 7,   Pages 915-925 doi: 10.1631/FITEE.2000141

Abstract: facilitates the generation of virtual environments for various scenarios about cities. It requires expertise and consideration, and therefore consumes massive time and computation resources. Nevertheless, related tasks sometimes result in dissatisfaction or even failure. These challenges have received significant attention from researchers in the area of . Meanwhile, the burgeoning development of artificial intelligence motivates people to exploit , and hence improves the conventional solutions. In this paper, we present a review of approaches to in using in the literature published between 2010 and 2019. This serves as an overview of the current state of research on from a perspective.

Keywords： 城市建模；计算机图形学；机器学习；深度学习    

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Thermal Effect Analysis of Frictional Disk in Speeding Wet Clutch

Hong Yue,Liu Jin,Wang Yungen

Strategic Study of CAE 2003, Volume 5, Issue 9,   Pages 55-60

Abstract:

Multi-frictional disks are employed to transmit the torque in speeding wet clutch, and the oil thickness within frictional disks could be adjusted for practical output speeding. As oil combined with a-hydrocarbon or polyester is getting widely used as lubricant and the speeding wet clutch works within hydrodynamic lubrication, mixture lubrication, boundary lubrication and contact situations, the authors have established the thermal analysis model for investigating the behavior of frictional disks in speeding wet clutch, which covers the power - law fluid model, Patir - Cheng average flow model, GT asperity contact model, oil film inertia and heat effects, mean energy equation, and heat conduction equation. The formulas in the model have been inferred in this paper. The numeral calculation and analysis for hydrodynamic lubrication and mixture lubrication have been executed.

Keywords： speeding wet clutch     thermal analysis     Reynolds equation     power-law fluid model     roughness    

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Issues on the Scalability in Designing a Massively Parallel Processor

Lu Xicheng

Strategic Study of CAE 2000, Volume 2, Issue 10,   Pages 105-109

Abstract:

The massively parallel processor (MPP) has been designed to meet the requirements for the high performance computing in many application fields of both national defense and economy. The structural scalability and the friendly programming are the two important and conflicting goals in designing a MPP system. Based on practice, the issues on the scalable design of MPPs are discussed in this paper.

Keywords： architecture     MPP     SMP     CC-NUMA     cluster     hypernode    

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The Basic Study for Quench Detection in Superconducting Electric Equipments

Yu Xiaoyan,Li Jingdong,Tang Yuejin

Strategic Study of CAE 2003, Volume 5, Issue 10,   Pages 73-77

Abstract:

Quench of superconducting electric equipments is an important problem for superconducting electric power systems and will affect its operation. This paper presents the quench detection of SMES in power system operation, and puts forward forecast theory for quench detection.

Keywords： superconducting electric equipments     quench detection     superconducting electric power system     forecast theory    

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Title Author Date Type Operation

基于非易失存储器的细粒度检查点

文喆 张,凯 卢,Mikel LUJAN,小平 王,旭 周

Journal Article

Versionized process based on non-volatile random-access memory for fine-grained fault tolerance

Wen-zhe ZHANG, Kai LU, Xiao-ping WANG

Journal Article

Zirconia quantum dots for a nonvolatile resistive random access memory device

Xiang-lei HE, Rui-jie TANG, Feng YANG, Mayameen S. KADHIM, Jie-xin WANG, Yuan PU, Dan WANG

Journal Article

Anovel non-volatile memory storage system for I/O-intensive applications

Wen-bing HAN, Xiao-gang CHEN, Shun-fen LI, Ge-zi LI, Zhi-tang SONG, Da-gang LI, Shi-yan CHEN

Journal Article

An efficient wear-leveling-aware multi-grained allocator for persistent memory file systems

Tao CAI, Pengfei GAO, Dejiao NIU, Yueming MA, Tianle LEI, Jianfei DAI,caitao@ujs.edu.cn,1306943800@qq.com

Journal Article

&

Yitian YANG, Youyou LU,yangyiti22@mails.tsinghua.edu.cn,luyouyou@tsinghua.edu.cn

Journal Article

Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory

Sutapa SARKAR, Biplab Kumar SIKDAR, Mousumi SAHA

Journal Article

Optimization Strategy of MPEG-4 AAC Decoder on a Low-cost SoC

Gao Gugang,Shi Longxing,Pu Hanlai,Zhou Fan

Journal Article

A BCH error correction scheme applied to FPGA with embedded memory

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Journal Article

MyWAL: performance optimization by removing redundant input/output stack in key-value store

Xiao ZHANG, Mengyu LI, Michael NGULUBE, Yonghao CHEN, Yiping ZHAO,zhangxiao@nwpu.edu.cn,limy@mail.nwpu.edu.cn

Journal Article

Research on Urban Mining Development in China

Sun Xiaofei,Qian Yi,Wen Zongguo,Liu Lili,Shan Guijuan and Li Jinhui

Journal Article

A review of computer graphics approaches to urban modeling from a machine learning perspective

Tian Feng, Feiyi Fan, Tomasz Bednarz,t.feng@latrobe.edu.au

Journal Article

Thermal Effect Analysis of Frictional Disk in Speeding Wet Clutch

Hong Yue,Liu Jin,Wang Yungen

Journal Article

Issues on the Scalability in Designing a Massively Parallel Processor

Lu Xicheng

Journal Article

The Basic Study for Quench Detection in Superconducting Electric Equipments

Yu Xiaoyan,Li Jingdong,Tang Yuejin

Journal Article