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Nagle algorithm and its application research in embedded Internet

Wang Baobao,Yu Shiming and Wang Zhenyu

Strategic Study of CAE 2014, Volume 16, Issue 2,   Pages 101-105

Abstract:

The existence of small packets in embedded Internet lead to low bandwidth efficiency and even congestion. The Nagle algorithm was applied by standard transmission control protocol（TCP）protocol to reduce the number of small packets. The paper builds embedded Internet network based on ARM7 32 bits micro control unit（MCU）and personal computer（PC）， analyses the principle and working mechanism of Nagle，and suggests an approach to resolve the temporary“deadlock”created by the interaction between the Nagle algorithm and the delayed ACK policy without modifying the Nagle algorithm through improving sampling frequency or filling the buffer in embedded system. The experimental results indicate that this approach is effective and reliable.

Keywords： Nagle algorithm     deadlock     delayed ACK policy     ARM7     embedded Internet    

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A Review of Recent Developments in “On-Chip” Embedded Cooling Technologies for Heterogeneous Integrated Applications Review

Srikanth Rangarajan, Scott Schiffres, Bahgat Sammakia

Engineering 2023, Volume 26, Issue 7,   Pages 185-197 doi: 10.1016/j.eng.2022.10.019

Abstract:

The electronics packaging community strongly believes that Moore’s law will continue for another few years due to recent technological efforts to build heterogeneously integrated packages. Heterogeneous integration (HI) can be at the chip level (a single chip with multiple hotspots), in multi-chip modules, or in vertically stacked three-dimensional (3D) integrated circuits. Flux values have increased exponentially with a simultaneous reduction in chip size and a significant increase in performance, leading to increased heat dissipation. The electronics industry and the academic research community have examined various solutions to tackle skyrocketing thermal-management challenges. Embedded cooling eliminates most sequential conduction resistance from the chip to the ambient, unlike separable cold plates/heat sinks. Although embedding the cooling solution onto an electronic chip results in a high heat transfer potential, technological risks and complexity are still associated with the implementation of these technologies and with uncertainty regarding which technologies will be adopted. This manuscript discusses recent advances in embedded cooling, fluid selection considerations, and conventional, immersion, and additive manufacturing-based embedded cooling technologies.

Keywords： Electronic cooling     Embedded cooling     Immersion cooling    

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An embedded lightweight GUI component library and ergonomics optimization method for industry process monitoring Research Articles

Da-peng TAN, Shu-ting CHEN, Guan-jun BAO, Li-bin ZHANG

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 5,   Pages 604-625 doi: 10.1631/FITEE.1601660

Abstract: Developing an efficient and robust lightweight graphic user interface (GUI) for industry process monitoring is always a challenging task. Current implementation methods for embedded GUI are with the matters of real-time processing and ergonomics performance. To address the issue, an embedded lightweight GUI component library design method based on quasar technology embedded (Qt/E) is proposed. First, an entity-relationship (E-R) model for the GUI library is developed to define the functional framework and data coupling relations. Second, a cross-compilation environment is constructed, and the Qt/E shared library files are tailored to satisfy the requirements of embedded target systems. Third, by using the signal-slot communication interfaces, a message mapping mechanism that does not require a call-back pointer is developed, and the context switching performance is improved. According to the multi-thread method, the parallel task processing capabilities for data collection, calculation, and display are enhanced, and the real-time performance and robustness are guaranteed. Finally, the human-computer interaction process is optimized by a scrolling page method, and the ergonomics performance is verified by the industrial psychology methods. Two numerical cases and five industrial experiments show that the proposed method can increase real-time read-write correction ratios by more than 26% and 29%, compared with Windows-CE-GUI and Android-GUI, respectively. The component library can be tailored to 900 KB and supports 12 hardware platforms. The average session switch time can be controlled within 0.6 s and six key indexes for ergonomics are verified by different industrial applications.

Keywords： Embedded lightweight graphic user interface (GUI)     Quasar technology embedded (Qt/E)     Industry process moni-toring     Multi-thread     Ergonomics performance    

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Design and Developing of the Network Device Driver on Embedded Access Point

Wang Zhili,Hu Aiqun,Song Yubo

Strategic Study of CAE 2005, Volume 7, Issue 10,   Pages 91-94

Abstract:

This paper systematically introduces the main structure of network device driver based on embedded Linux. With the PCMCIA API, the software modules of embedded AP (access point) and the developing course are stressed. The testing results of the network device driver are given at the end of the paper.

Keywords： embedded linux     network device driver     PCMCIA    

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The Design and Analysis of Embedded Internet Control System

Zong Qun,Li Ran,Wang Bo

Strategic Study of CAE 2005, Volume 7, Issue 5,   Pages 53-56

Abstract:

An embedded Internet control system with embedded Internet nodes, of which the requirements and architecture is analyzed and studied, has been built up successfully and put into practice in REMS. Then the whole system is fully tested to prove that it can meet with the practical requirements well.

Keywords： embedded Internet control system     REMS     DS80C400     JAVA     TINI    

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BORON: an ultra-lightweight and low power encryption design for pervasive computing Article

Gaurav BANSOD,Narayan PISHAROTY,Abhijit PATIL

Frontiers of Information Technology & Electronic Engineering 2017, Volume 18, Issue 3,   Pages 317-331 doi: 10.1631/FITEE.1500415

Abstract: We propose an ultra-lightweight, compact, and low power block cipher BORON. BORON is a substitution and permutation based network, which operates on a 64-bit plain text and supports a key length of 128/80 bits. BORON has a compact structure which requires 1939 gate equivalents (GEs) for a 128-bit key and 1626 GEs for an 80-bit key. The BORON cipher includes shift operators, round permutation layers, and XOR operations. Its unique design helps generate a large number of active S-boxes in fewer rounds, which thwarts the linear and differential attacks on the cipher. BORON shows good performance on both hardware and software platforms. BORON consumes less power as compared to the lightweight cipher LED and it has a higher throughput as compared to other existing SP network ciphers. We also present the security analysis of BORON and its performance as an ultra-lightweight compact cipher. BORON is a well-suited cipher design for applications where both a small footprint area and low power dissipation play a crucial role.

Keywords： Lightweight cryptography     SP network     Block cipher     Internet of Things (IoT)     Encryption     Embedded security    

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Non-iterative parameter estimation of the 2R-1Cmodel suitable for low-cost embedded hardware Article

Mitar SIMIĆ, Zdenka BABIĆ, Vladimir RISOJEVIĆ, Goran M. STOJANOVIĆ

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 3,   Pages 476-490 doi: 10.1631/FITEE.1900112

Abstract: Parameter estimation of the 2R-1C model is usually performed using iterative methods that require high-performance processing units. Consequently, there is a strong motivation to develop less time-consuming and more power-efficient parameter estimation methods. Such low-complexity algorithms would be suitable for implementation in portable microcontroller-based devices. In this study, we propose the quadratic interpolation non-iterative parameter estimation (QINIPE) method, based on quadratic interpolation of the imaginary part of the measured impedance, which enables more accurate estimation of the characteristic frequency. The 2R-1C model parameters are subsequently calculated from the real and imaginary parts of the measured impedance using a set of closed-form expressions. Comparative analysis conducted on the impedance data of the 2R-1C model obtained in both simulation and measurements shows that the proposed QINIPE method reduces the number of required measurement points by 80% in comparison with our previously reported non-iterative parameter estimation (NIPE) method, while keeping the relative estimation error to less than 1% for all estimated parameters. Both non-iterative methods are implemented on a microcontroller-based device; the estimation accuracy, RAM, flash memory usage, and execution time are monitored. Experiments show that the QINIPE method slightly increases the execution time by 0.576 ms (about 6.7%), and requires 24% (1.2 KB) more flash memory and just 2.4% (32 bytes) more RAM in comparison to the NIPE method. However, the impedance root mean square errors (RMSEs) of the QINIPE method are decreased to 42.8% (for the real part) and 64.5% (for the imaginary part) of the corresponding RMSEs obtained using the NIPE method. Moreover, we compared the QINIPE and the complex nonlinear least squares (CNLS) estimation of the 2R-1C model parameters. The results obtained show that although the estimation accuracy of the QINIPE is somewhat lower than the estimation accuracy of the CNLS, it is still satisfactory for many practical purposes and its execution time reduces to 145−1 30.

Keywords： 2R-1C model     Embedded systems     Parameter estimation     Non-iterative methods     Quadratic interpolation    

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Implementation of PRINCE with resource-efficient structures based on FPGAs Research Articles

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 11,   Pages 1505-1516 doi: 10.1631/FITEE.2000688

Abstract: In this era of pervasive computing, low-resource devices have been deployed in various fields. is a designed for low latency, and is suitable for pervasive computing applications. In this paper, we propose new circuit structures for components by sharing and simplifying logic circuits, to achieve the goal of using a smaller number of logic gates to obtain the same result. Based on the new circuit structures of components and the best sharing among components, we propose three new hardware architectures for . The architectures are simulated and synthesized on different programmable gate array devices. The results on Virtex-6 show that compared with existing architectures, the resource consumption of the unrolled, , and two-cycle architectures is reduced by 73, 119, and 380 slices, respectively. The architecture costs only 137 slices. The unrolled architecture costs 409 slices and has a throughput of 5.34 Gb/s. To our knowledge, for the hardware implementation of , the new architecture sets new area records, and the new unrolled architecture sets new throughput records. Therefore, the newly proposed architectures are more resource-efficient and suitable for lightweight, latency-critical applications.

Keywords： 轻量级分组密码；现场可编程门阵列（FPGA）；低成本；PRINCE；嵌入式安全    

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Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA Personal View

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Frontiers of Information Technology & Electronic Engineering 2020, Volume 21, Issue 4,   Pages 615-628 doi: 10.1631/FITEE.1800681

Abstract: Since the dawn of the Internet of Things (IoT), data and system security has been the major concern for developers. Because most IoT devices operate on 8-bit controllers with limited storage and computation power, encryption and decryption need to be implemented at the transmitting and receiving ends, respectively, using lightweight ciphers. We present novel architectures for hardware implementation for the ANU cipher and present results associated with each architecture. The ANU cipher is implemented at 4-, 8-, 16-, and 32-bit datapath sizes on four different field-programmable gate array (FPGA) platforms under the same implementation condition, and the results are compared on every performance metric. Unlike previous ANU architectures, the new architectures have parallel substitution boxes (S-boxes) for high throughput and hardware optimization. With these different datapath designs, ANU cipher proves to be the obvious choice for implementing security in extremely resourceconstrained systems.

Keywords： Lightweight cryptography     Internet of Things (IoT)     Embedded security     Encryption     FPGA     Datapath design    

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Design of GPRS Data Terminal Based on S3C2410

Sun Xueyong

Strategic Study of CAE 2007, Volume 9, Issue 12,   Pages 94-96

Abstract: This paper discusses the hardware structure and working process of the embedded Internetconnected platform, which regards S3C2410 as kernel and SIM100-E as GPRS communication module. Then the software hierarchy is described and the realization of PPP dialup software package based on this platform is explained in detail.

Keywords： GPRS；embedded Internet；S3C2410；SIM100-E    

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Research of Lossless Image Compression Base on Level-scalability

Li Luwei,Zhou Shuoyan,Cai Yiyu

Strategic Study of CAE 2005, Volume 7, Issue 10,   Pages 33-37

Abstract:

A level-embedded lossless image compression method for continuous-tone still images is presented. Level (bit-plane) scalability is achieved by separating the image into two layers (the base layer and the residual layer) before compression. Excellent compression performance is obtained by exploiting both spatial and interlevel correlations. A comparison of the proposed scheme with a number of scalable and non-scalable lossless image compression algorithms indicates that the level-embedded compression incurs only a small penalty in compression efficiency over non-scalable lossless compression, while offering the significant benefit of level-scalability.

Keywords： data processing techniques     lossless image compression     context-based model     embedded level    

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Hardware Module of Multi-Protocol Tester Based on the Specification of 2.0 Mb/s High Speed Signalling link

Liu Zhihui

Strategic Study of CAE 2002, Volume 4, Issue 2,   Pages 79-85

Abstract:

Great progress has been made in the information industry of the world. Protocol and signalling are becoming more and more important. Telecommunication equipments and instruments are the very guarantee for information industry. Following the development of mobile communication and intelligence network, the 64 kb/s No.7 signalling link now used is no longer suitable for the service increasement. The 2.048Mb/s high speed signalling link has become the best substitude. Since there is no related protocol testing equipment used for telecommunication branch, The 2.048 Mb/s high speed signalling protocol-analyzing set is developed for this purpose. In order to ensure the quality of the analyzing set, the best embedded processor and newest real time operating system are employed.

Keywords： 2.048 Mb/s high speed signalling link     embedded processor     real time operating system     protocol-analyzing set    

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A BCH error correction scheme applied to FPGA with embedded memory Research Articles

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Frontiers of Information Technology & Electronic Engineering 2021, Volume 22, Issue 8,   Pages 1127-1139 doi: 10.1631/FITEE.2000323

Abstract: Given the potential for bit flipping of data on a memory medium, a high-speed parallel Hocquenghem (BCH) error correction scheme with modular characteristics, combining logic implementation and a look-up table, is proposed. It is suitable for data error correction on a modern field programmable gate array full with on-chip embedded memories. We elaborate on the optimization method for each part of the system and analyze the realization process of this scheme in the case of the BCH code with an information bit length of 1024 bits and a code length of 1068 bits that corrects the 4-bit error.

Keywords： 纠错算法；Bose–Chaudhuri–Hocquenghem（BCH）码；现场可编程门阵列（FPGA）；闪存    

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Chaotic digital cryptosystem using serial peripheral interface protocol and its dsPIC implementation None

Rodrigo MÉNDEZ-RAMÍREZ, Adrian ARELLANO-DELGADO, César CRUZ-HERNÁNDEZ, Fausto ABUNDIZ-PÉREZ, Rigoberto MARTÍNEZ-CLARK

Frontiers of Information Technology & Electronic Engineering 2018, Volume 19, Issue 2,   Pages 165-179 doi: 10.1631/FITEE.1601346

Abstract: The current massive use of digital communications demands a secure link by using an embedded system (ES) with data encryption at the protocol level. The serial peripheral interface (SPI) protocol is commonly used by manufacturers of ESs and integrated circuits for applications in areas such as wired and wireless communications. We present the design and experimental implementation of a chaotic encryption and decryption algorithm applied to the SPI communication protocol. The design of the chaotic encryption algorithm along with its counterpart in the decryption is based on the chaotic Hénon map and two methods for blur and permute (in combination with DNA sequences). The SPI protocol is configured in 16 bits to synchronize a transmitter and a receiver considering a symmetric key. Results are experimentally proved using two low-cost dsPIC microcontrollers as ESs. The SPI digital-to-analog converter is used to process, acquire, and reconstruct confidential messages based on its properties for digital signal processing. Finally, security of the cryptogram is proved by a statistical test. The digital processing capacity of the algorithm is validated by dsPIC microcontrollers.

Keywords： Chaotic systems     Statistical tests     Embedded systems     dsPIC microcontroller     Serial peripheral interface (SPI) protocol    

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Design and Occupant-Protection Performance Analysis of a New Tubular Driver Airbag Article

Huajian Zhou, Zhihua Zhong, Manjiang Hu

Engineering 2018, Volume 4, Issue 2,   Pages 291-297 doi: 10.1016/j.eng.2018.03.015

Abstract:

An airbag is an effective protective device for vehicle occupant safety, but may cause unexpected injury from the excessive energy of ignition when it is deployed. This paper focuses on the design of a new tubular driver airbag from the perspective of reducing the dosage of gas generant. Three different dummies were selected for computer simulation to investigate the stiffness and protection performance of the new airbag. Next, a multi-objective optimization of the 50th percentile dummy was conducted. The results show that the static volume of the new airbag is only about 1/3 of the volume of an ordinary one, and the injury value of each type of dummy can meet legal requirements while reducing the gas dosage by at least 30%. The combined injury index (Pcomb) decreases by 22% and the gas dosage is reduced by 32% after optimization. This study demonstrates that the new tubular driver airbag has great potential for protection in terms of reducing the gas dosage.

Keywords： New tubular airbag     Occupant protection     Multi-objective optimization    

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Title Author Date Type Operation

Nagle algorithm and its application research in embedded Internet

Wang Baobao,Yu Shiming and Wang Zhenyu

Journal Article

A Review of Recent Developments in “On-Chip” Embedded Cooling Technologies for Heterogeneous Integrated Applications

Srikanth Rangarajan, Scott Schiffres, Bahgat Sammakia

Journal Article

An embedded lightweight GUI component library and ergonomics optimization method for industry process monitoring

Da-peng TAN, Shu-ting CHEN, Guan-jun BAO, Li-bin ZHANG

Journal Article

Design and Developing of the Network Device Driver on Embedded Access Point

Wang Zhili,Hu Aiqun,Song Yubo

Journal Article

The Design and Analysis of Embedded Internet Control System

Zong Qun,Li Ran,Wang Bo

Journal Article

BORON: an ultra-lightweight and low power encryption design for pervasive computing

Gaurav BANSOD,Narayan PISHAROTY,Abhijit PATIL

Journal Article

Non-iterative parameter estimation of the 2R-1Cmodel suitable for low-cost embedded hardware

Mitar SIMIĆ, Zdenka BABIĆ, Vladimir RISOJEVIĆ, Goran M. STOJANOVIĆ

Journal Article

Implementation of PRINCE with resource-efficient structures based on FPGAs

Lang Li, Jingya Feng, Botao Liu, Ying Guo, Qiuping Li,lilang911@126.com,fengjyk@126.com

Journal Article

Design and implementation of various datapath architectures for the ANU lightweight cipher on an FPGA

Vijay DAHIPHALE, Gaurav BANSOD, Ankur ZAMBARE, Narayan PISHAROTY

Journal Article

Design of GPRS Data Terminal Based on S3C2410

Sun Xueyong

Journal Article

Research of Lossless Image Compression Base on Level-scalability

Li Luwei,Zhou Shuoyan,Cai Yiyu

Journal Article

Hardware Module of Multi-Protocol Tester Based on the Specification of 2.0 Mb/s High Speed Signalling link

Liu Zhihui

Journal Article

A BCH error correction scheme applied to FPGA with embedded memory

Yang Liu, Jie Li, Han Wang, Debiao Zhang, Kaiqiang Feng, Jinqiang Li,lylyly357@163.com,lijie@nuc.edu.cn

Journal Article

Chaotic digital cryptosystem using serial peripheral interface protocol and its dsPIC implementation

Rodrigo MÉNDEZ-RAMÍREZ, Adrian ARELLANO-DELGADO, César CRUZ-HERNÁNDEZ, Fausto ABUNDIZ-PÉREZ, Rigoberto MARTÍNEZ-CLARK

Journal Article

Design and Occupant-Protection Performance Analysis of a New Tubular Driver Airbag

Huajian Zhou, Zhihua Zhong, Manjiang Hu

Journal Article